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Mosfet
1. NT 2005 MOLECULAR AND
NANOELECTRONICS
MOSFET
BY,
A. POOJA SHUKLA
1821310006
M. Tech (I year)
2. INTRODUCTION TO
TRANSISTOR
In 1947 by John Bardeen, Walter Brattain and William Shockley
the transistor revolutionized the field of electronics
A transistor is a semiconductor device used to amplify and switch
electronic signals and electrical power.
It is composed of semiconductor material with at least three
terminals for connection to an external circuit.
The transistor is the fundamental building block of modern
electronic devices.
6. WHAT IS MOSFET….???
The
metal–oxide–semiconductor
field-effect
transistor
(MOSFET, MOS-FET, or MOS FET) is a transistor used for
amplifying or switching electronic signals.
11. MOSFET STRUCTURE
• This device is symmetric, so either of the n+ regions can be source
or drain.
12. INTO TO FABRICATION…..!!!
•
Photolithography (photo)
–
Process of transferring pattern on mask to photoresist layer on wafer surface (pre-pattern the
chip)
•
Etching
–
Process of permanently removed the unwanted part of design on wafer surface to get the
desired pattern
•
Diffusion
–
Process of introducing dophant layer by movement of dophant atoms from high concentration
to low concentration area at high temperature
•
Ion implantation
–
Process of introducing dophant layer by bombardment of high energy dophant ion in high
electric field chamber
•
Oxidation
–
•
Process of growing thick or thin SiO2 layer depend on oxide application
CMP
–
Process to physically grind flat to have a planar surface for better exposure at photo process.
19. MOSFET OPERATION
Step 1: Apply Gate Voltage
SiO2 Insulator (Glass)
Gate
Source
Drain
5 volts
holes
N
N
electrons
P
electrons to be
transmitted
Step 2: Excess electrons surface in
channel, holes are repelled.
Step 3: Channel becomes saturated
with electrons. Electrons in source
are able to flow across channel to
Drain.
20. N-MOSFET
– 4 electrical terminals
• Source
• Drain
• Gate
• Substrate
– Connected to Gnd
Gate
Source
Drain
Substrate (Body)
– Source and drain are only different in their interpretation
• Terminal with lower voltage is the source (by convention)
– Simplified symbol omits the substrate
VG
VS
VD
22. N-MOSFET
• NMOS Behavior
– When Gate (VG) is high (i.e. 1) the NMOS transistor acts as a
closed switch
• When VG = 0, the NMOS transistor is an open switch
VG
VS
VG = "low"
VD
VG = "high"
23. P-MOSFET
– Same 4 electrical terminals
• Source
• Drain
• Gate
• Substrate
– Connected to VDD
Gate
Drain
Substrate (Body)
Source
V DD
– Again, source and drain are only different in their interpretation
• Terminal with higher voltage is the source (by convention)
– Simplified symbol omits the substrate
VG
VS
VD
25. P-MOSFET
• PMOS Behavior
– When Gate (VG) is low (i.e. 0) the PMOS transistor acts as a closed
switch
• When VG = 1, the PMOS transistor is an open switch
VG
VS
VG = "high"
VD
VG = "low"
26. CMOSFET PROCESS FLOW
WELL FORMATION
ISOLATION FORMATION
TRANSISTOR MAKING
INTERCONNECTION
PASSIVATION
30. CMOS FABRICATION PROCESS
well formation
Well will be formed
here
• By *photolithography and etching process, well
opening are made
*photolithography and etch processes are shown in next slides
31. CMOS FABRICATION PROCESS
photoresist
Si02
P-substrate
• Photoresist coating (C)
UV light
• Masking and exposure under UV
mask
Opaque
area
P-substrate
Transparent
area
light(E)
• Resist dissolved after developed (D)
– Pre-shape the well pattern at resist
layer
32. ETCHING
• Removing the unwanted
P-substrate
P-substrate
pattern by wet etching
• Resist clean
• Desired pattern formed
33. CMOS FABRICATION PROCESS
well formation
Phosphorus ion
• Ion bombardment by ion implantation
• SiO2 as mask, uncovered area will exposed to dophant ion
34. CMOS FABRICATION PROCESS
isolation formation
Thick oxide
• Increase SiO2 thickness by oxidation at high
temperature
• Oxide will electrically isolates nmos and pmos devices
35. CMOS FABRICATION PROCESS
transistor making
nmos will be
formed here
pmos will be
formed here
LOCOS (isolation structure)
• By photolithography and etching process,
pmos and nmos areas are defined
39. CMOS FABRICATION PROCESS
transistor making
Arsenic ion
photoresist
• Photo process to define the nmos’s active (source
and drain) area and VDD contact
• Ion implantation with Arsenic ion for n+ dophant.
• Photoresist and polisilicon gate act as mask
41. CMOS FABRICATION PROCESS
transistor making
Boron ion
photoresist
• Photo process to define the GND contact and pmos’s active
area (source and drain)
• Ion implantation with boron ionto have p+ dophant
• Photoresist and gate act as mask
42. CMOS FABRICATION PROCESS
transistor making
GND
contact
Pmos’s
drain
Pmos’
source
• Pmos’s source and drain formation with GND
contact
• Resist removal
