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AMD: Where Gaming Begins

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AMD
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This document describes the architecture of a superscalar out-of-order processor core. It can dispatch up to 6 macro operations per cycle and execute up to 4 instructions per cycle. It has an 8-way issue width and can perform up to 3 loads and 2 stores per cycle.

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◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢
◢ ◢ ◢ ◢ 8 Way8 Way 3 LOADS PER CYCLE 2 STORES PER CYCLE
◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢
4 Instructions/Cycle 8 Way8 Way 8 Way 8 Macro/Ops Cycle 3 LOADS PER CYCLE 2 STORES PER CYCLE 6 Macro Ops/Cycle Dispatched ◢ ◢ ◢ ◢ ◢
◢ ◢ ◢ ◢ ◢ ◢
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◢ ◢ ◢ ◢
◢ ◢ ◢ ◢ 4 Instructions/Cycle 8 Way 8 Macro Ops/Cycle 6 Macro Ops/Cycle Dispatched
◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢ ◢
3 Load 2 Store ◢ ◢ ◢ ◢ ◢ ◢ ◢
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