In this presentation we explain the rationale behind the FPGA. Discoveries associated with a more precise comprehension of the connections inside human brain are foreseen as disruptive in many fields: from improved neurological disorders treatment to strong artificial intelligence, as well as more precise and less invasive diagnostic tools and, finally, improved Big Data systems. For this purpose, Brain Networks (BNs) are used to quickly and accurately model and map neural interconnections inside human brain. A common statistical tool that helps analysis and definition of BNs is the Pearson Correlation Coefficient (PCC), which is able to identify the correlation between neurons or groups of neighboring neurons. However, the computational power that commonly available technologies provide allows scientists to analyze only few hundred neural nodes within reasonable time. Increasing the number of analyzed neurons and speeding up the computation are both fundamental steps to achieve more accurate results, and to allow the scientific and medical research to progress. This work presents an implementation of BNs on Xilinx VIRTEX-7 FPGA. Our goal is to tackle the problems previously described, in order to provide a fast hardware implementation able to support the computation of a remarkable number of neurons.

1. Brain NECSTworkEleonora D'Arnese
eleonora.darnese@mail.polimi.it
Enrico Reggiani
enrico2.reggiani@mail.polimi.it
Marco Gucciardi
marco.gucciardi@mail.polimi.it
image from http://i1-news.softpedia-static.com/images/news2/The-Brain-Super-Sized-Computer-Going-from-Internet-to-Fiber-Optics-2.jpg

2. Brain NECSTwork
• Extraction of brain features
from functional Magnetic
Resonance Imaging
• Analysis of the data
• Creation of significant images
for diagnosis and medical
research
2
http://today.uconn.edu/wp-content/uploads/2014/01/fmri-2.jpg

3. Brain NECSTwork
• Extraction of brain features
from functional Magnetic
Resonance Imaging
• Analysis of the data
• Creation of significant images
for diagnosis and medical
research
2
http://today.uconn.edu/wp-content/uploads/2014/01/fmri-2.jpg
http://cdni.wired.co.uk/1240x826/a_c/Brain_11.jpg

4. 3
Analizing the code: Serial vs Parallel
• Analysis based on Pearson Correlation Coefficient
– Same computation for all the pixels
– Parallel architecture is suitable
Serial Parallel

5. 3
Analizing the code: Serial vs Parallel
• Analysis based on Pearson Correlation Coefficient
– Same computation for all the pixels
– Parallel architecture is suitable
Serial Parallel

6. 3
A Concrete Example
From the analysis
• The FPGA gains a 2x speedup w.r.t. GPU implementation
• FPGA is able to maintain real time analysis (1s) even with the highest resolution
“On how to efficiently accelerate brain network analysis on FPGA-based computing system”, G. Gnemmi, M. Crippa, G. Durelli, R.
Cattaneo, G. Pallotta, M. D. Santambrogio; IEEE, 2015

7. 4
A Concrete Example
From previous analysis
• Virtex requires a lower energetic amount for a single correlation calculation
compared to the other choices
“On how to efficiently accelerate brain network analysis on FPGA-based computing system”, G. Gnemmi, M. Crippa, G.
Durelli, R. Cattaneo, G. Pallotta, M. D. Santambrogio; IEEE, 2015

8. 6
ASIC: possible solution but...
• An ASIC-based solution
would be better for
– Execution time
– Energy efficiency
• However
– Time to market is too high
– Final cost would be not
competitive
http://www.legitreviews.com/images/revi
ews/1310/seagate_asic.jpg
http://elettronica-plus.it/wp-
content/uploads/sites/2/2011/07/xilinx21.jpg

9. Eleonora D’Arnese – eleonora.darnese@mail.polimi.it
Enrico Reggiani – enrico2.reggiani@mail.polimi.it
Marco Gucciardi – marco.gucciardi@mail.polimi.it
https://m.facebook.com/BrainNECSTwork
https://twitter.com/Brain_NECSTwork?s=08
http://www.slideshare.net/BrainNECSTwork
Contacts