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4-Bit Counter
Design and Simulation using Microwind,
Dsch3.0 and Spice
Mr. Nayyer Abbas Hira Shaukat 2010131
OBJECTIVE
“The purpose of this project is to design with
Microwind a 4-bit asynchronous counter with a
reset function.”
BLOCK DIAGRAM
•Transistor
level
•Microwind
NOT Gate
•DSCH
•Microwind
Complex Gate
•DSCH
•Microwind
D Latch
•By compiling
e...
Design Details
NOT Gate
• One NMOS and one PMOS is required
• Gates are interconnected to do the input
• Sources are interconnected to do...
NOT Gate (Schematic Diagram)
NOT Gate (Microwind design)
Layout of the NOT Gate (Microwind)
Complex Gate
• Compressed and optimized design
• Error in the design of paper
• Design characteristics do not need to be
f...
Complex Gate
Complex Gate (Schematic Diagram)
Schematic diagram of a complex gate
Complex Gate (Microwind design)
Layout of a complex gate (Microwind)
D Latch
• D Latch is designed using two Complex Gates
and one Inverter
D Latch (Schematic Diagram)
D Latch (Microwind Design)
Layout of a D Latch (Microwind)
D Register
• Master-Slave structure is chosen
• 2 D Latches and a NOT Gate is used to get a
single design
D Register (Schematic Diagram)
D Register (Microwind Design)
COUNTER
• 4 D Registers are cascaded
• Output of previous register is given to the
clock of next register
Counter (Schematic Diagram)
Counter (Microwind Design)
The End
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4 bit counter

  1. 1. 4-Bit Counter Design and Simulation using Microwind, Dsch3.0 and Spice Mr. Nayyer Abbas Hira Shaukat 2010131
  2. 2. OBJECTIVE “The purpose of this project is to design with Microwind a 4-bit asynchronous counter with a reset function.”
  3. 3. BLOCK DIAGRAM •Transistor level •Microwind NOT Gate •DSCH •Microwind Complex Gate •DSCH •Microwind D Latch •By compiling earlier layouts D-Register •Cascading D- Registers Counter
  4. 4. Design Details
  5. 5. NOT Gate • One NMOS and one PMOS is required • Gates are interconnected to do the input • Sources are interconnected to do the output
  6. 6. NOT Gate (Schematic Diagram)
  7. 7. NOT Gate (Microwind design) Layout of the NOT Gate (Microwind)
  8. 8. Complex Gate • Compressed and optimized design • Error in the design of paper • Design characteristics do not need to be followed
  9. 9. Complex Gate
  10. 10. Complex Gate (Schematic Diagram) Schematic diagram of a complex gate
  11. 11. Complex Gate (Microwind design) Layout of a complex gate (Microwind)
  12. 12. D Latch • D Latch is designed using two Complex Gates and one Inverter
  13. 13. D Latch (Schematic Diagram)
  14. 14. D Latch (Microwind Design) Layout of a D Latch (Microwind)
  15. 15. D Register • Master-Slave structure is chosen • 2 D Latches and a NOT Gate is used to get a single design
  16. 16. D Register (Schematic Diagram)
  17. 17. D Register (Microwind Design)
  18. 18. COUNTER • 4 D Registers are cascaded • Output of previous register is given to the clock of next register
  19. 19. Counter (Schematic Diagram)
  20. 20. Counter (Microwind Design)
  21. 21. The End
  • MohammadRezaKoopaei

    Jul. 17, 2020
  • jannatulferdous78

    Jul. 18, 2017
  • PantSpare

    Jan. 25, 2016
  • tajinderjhally

    Oct. 7, 2015

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