IBM scientists for the first time demonstrated a hybrid storage and caching subsystem, code-named Project Theseus, at the recent 2014 Non-Volatile Memories Workshop in San Francisco, California. And the amazing achievement is that they were using two year old PCM chip prototypes.
18. PCM Write Latency Distribution
Experimental parameters:
• Random data
• 32 sectors per write cycle
• 4 PCM channels
• 8 PCM banks/controllers
• Pipeline is active
Experiment
- Perform 10K write cycles with random data
(x32 sectors)
- Write, read and compare a set of 32 sectors
(single write cycle)
PCM is emerging as one of the most promising NVM technologies and is becoming more and more matureThe active material in PCM is a chalcogenidic alloy which is placed between two electrically conducting electrodes in each cell of the memory array.A low current is then applied that causes a phase transition.
We focus on a PCM-based system that uses PCM in a persistent storage device attached on the I/O bus of the system
One of the main concerns regarding the use of PCM for high-performance applications is its relatively high write latency. The purpose of this work has been to architect a PCM-based device and implement a fully functional, high-performance PCI-e card that takes advantage of the characteristics of PCM and mitigates its limitations. \The design of PSS targets storage workloads that are dominated by small (e.g., 4 kB) random I/O operations and aims to achieve low, predictable latency with reads and writes
Was commercially available when the project started (end of 2012)