1. ENGIN 112
Intro to Electrical and Computer
Engineering
Lecture 26
Shift Registers
ENGIN112 L26: Shift Registers November 3, 2003
2. Overvie
w
° Multiple flip flops can be combined to form a data
register
° Shift registers allow data to be transported one bit at a
time
° Registers also allow for parallel transfer
• Many bits transferred at the same time
° Shift registers can be used with adders to build
arithmetic units
° Remember: most digital hardware can be built from
combinational logic (and, or, invert) and flip flops
• Basic components of most computers
ENGIN112 L26: Shift Registers November 3, 2003
3. Reg
iste
°rRegister: Group of Flip-Flops
with
°Par D Flip-Flops
Ex:
allel
°Loa
Holds a Word (Nibble) of Data
°dLoads in Parallel on Clock
Transition
° Asynchronous Clear (Reset)
ENGIN112 L26: Shift Registers November 3, 2003
4. Reg
iste
°r Load Control = 1
with
•
Loa New data loaded
on next positive
d clock edge
Con
°trol Control = 0
Load
• Old data reloaded
on next positive
clock edge
ENGIN112 L26: Shift Registers November 3, 2003
5. Shif
t
°Reg
Cascade chain of Flip-Flops
iste
°rs
Bits travel on Clock edges
° Serial in – Serial out, can also have parallel load /
read
ENGIN112 L26: Shift Registers November 3, 2003
6. Parallel Data
Transfer
° All data transfers on rising clock edge
° Data clocked into register Y
ENGIN112 L26: Shift Registers November 3, 2003
7. Par
allel
ver
° sus communications is defined as
Serial
Seri
• Provides a binary number as a sequence of binary digits, one
al after another, through one data line.
° Parallel communications
• Provides a binary number through multiple data lines at the
same time.
ENGIN112 L26: Shift Registers November 3, 2003
8. Shif
t
°regi
Parallel-to-serial conversion for serial transmission
ster
app
licat
ion
parallel outputs
parallel inputs
serial transmission
ENGIN112 L26: Shift Registers November 3, 2003
9. Seri
al
° Data transfer one bit at a time
Tra
° nsf loopback for register A
Data
er
Time Reg A Reg B
T0 1011 0011
T1 1101 1001
T2 1110 1100
T3 0111 0110
T4 1011 1011
ENGIN112 L26: Shift Registers November 3, 2003
10. Serial Transfer of
Data
° Transfer from register X to register Y (negative
clock edges for this example)
ENGIN112 L26: Shift Registers November 3, 2003
11. Patt
ern
° Combinational function of input samples
recin this case, recognizing the pattern 1001 on the single input
•
ogn signal
izer
OUT
OUT1 OUT2 OUT3 OUT4
IN D Q D Q D Q D Q
CLK
Clk IN OUT1 OUT2 OUT3 OUT4 OUT
Before
1 1 0 0 0 0 0
2 0 1 0 0 0 0
3 0 0 1 0 0 0
4 1 0 0 1 0 0
5 0 1 0 0 1 1
ENGIN112 L26: Shift Registers November 3, 2003
12. Seri
al
°Add
Slower than
itio
parallel
n (D
°Flip cost
Low
-
°Flo
Share fast
hardware on
p)slow data
° Good for
multiplexed
data
ENGIN112 L26: Shift Registers November 3, 2003
13. Seri
al
Add
° Only one full
itio
adder
n (D
° Reused for
Flip
each bit
-
Flo
° Start with low-
p)
order bit
addition
° Note that carry
(Q) is saved
° Add multiple
values.
• New values
placed in shift
register B
ENGIN112 L26: Shift Registers November 3, 2003
14. Seri
al
Add
° Shift control
itio
used to stop
n (D
addition
Flip
° Generally not a
-
good idea to
Flo
gate the clock
p)
° Shift register
can be
arbitrary length
° FA can be built
from combin.
logic
ENGIN112 L26: Shift Registers November 3, 2003
15. Uni
ver
° sal
Clear
Shif
° Clock
t
° Reg
Shift
iste Right
•
r • Left
° Load
° Read
° Control
ENGIN112 L26: Shift Registers November 3, 2003
16. Design of Universal Shift
Register
° Consider one of the four
flip-flops clear s0 s1 new value
• new value at next clock 1 – – 0
0 0 0 output
cycle: 0 0 1 output value of FF to left (shift right)
0 1 0 output value of FF to right (shift left)
° Note slightly different 0 1 1 input
than Mano version Q[N]
(Clear) Nth cell
to N-1th to N+1th
cell Q cell
D
CLK
CLEAR
0 1 2 3 s0 and s1
control mux
Q[N-1] Q[N+1]
(left) Input[N] (right)
ENGIN112 L26: Shift Registers November 3, 2003
17. Summary
° Shift registers can be combined together to allow for
data transfer
° Serial transfer used in modems and computer
peripherals (e.g. mouse)
° D flip flops allow for a simple design
• Data clocked in during clock transition (rising or falling edge)
° Serial addition takes less chip area but is slow
° Universal shift register allows for many operations
• The register is programmable.
• It allows for different operations at different times
° Next time: counters (circuits that count!)
ENGIN112 L26: Shift Registers November 3, 2003
Editor's Notes
Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall
credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
