WorkRTL DESIGN VERIFICATION BY SV AND UVM course completed, looking for job in vlsi domain
About SUMMARY OF SKILLS
• Qualified B.E. (Electronics & Communication) from P.A College of Engineering (VTU); Pursued RTL DESIGN VERIFICATION BY SV AND UVM course.
• Possess comprehensive knowledge & hands on experience in Verilog HDL, System Verilog , UVM Basics
• Good understanding in developing Verification Environment from Specification
• Good understanding of Code coverage & Functional Coverage .
• Strong communication and presentation skills with the ability to perform above expectations.
• Hardware Description Language: Verilog HDL, System Verilog, UVM Basics
• Protocol Knowledge: AMBA-APB
• EDA Tools Used: QuestaSim, Mode...