1. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Colorado Technical University
PSpice, L-Edit Designed CMOS NAND Gate Analysis
Lab 6 Report
Submitted to Professor R. Hoffmeister
In Partial Fulfillment of the Requirements for
EE 325-CMOS Design
By
Loren Karl Robinson Schwappach
Student Number: 06B7050651
Colorado Springs, Colorado
Due: 7 June 2010
Completed: 11 June 2010
1

2. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Table of Contents
Lab Objectives ........................................................................................................................................................................................ 3
Requirements and Design Approaches/Trade-Offs................................................................................................................... 3
L-Edit CMOS NAND Gate ................................................................................................................................................................... 4-
CMOS NAND Gate Design Details................................................................................................................................. 4-5
CMOS NAND Gate Cross Sections .................................................................................................................................... 6
CMOS NAND Gate Design Rule Check ............................................................................................................................ 6
CMOS NAND Gate L-Edit Extracted NAND.SPC File .................................................................................................. 7
CMOS NAND Gate Modified SCNA.SPC File .................................................................................................................. 8
CMOS NAND Gate Test Plan .............................................................................................................................................. 8
Fairchild Semiconductor CD4011BC Quad 2-Input NAND Buffered B Series Gate Characteristics .......................... 9
Table of Characteristics ................................................................................................................................................... 10
Voltage Transfer Function of the L-Edit CMOS NAND Gate ................................................................................................ 11
Circuit Layout...................................................................................................................................................................... 12
PSpice Simulation Results......................................................................................................................................... 13-14
Truth Table Simulation Results .................................................................................................................................... 15
Truth Table .......................................................................................................................................................................... 16
Propagation Delay and Rise/Fall Times of the CMOS NAND Gate .................................................................................... 17
Circuit Layouts.................................................................................................................................................................... 17
PSpice Simulation Results......................................................................................................................................... 18-19
Summary of Results ........................................................................................................................................................................... 20
Conclusion and Recommendations .............................................................................................................................................. 21
2

3. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Lab Objectives
The objective of this lab is to translate a usable CMOS NAND gate into a physical Integrated
Circuit (IC) design layout, useable by PSpice through the use of L-Edit software. The device
must have a delay of less than 50 ns while carrying a 10 pF load capacitance. Finally, the L-
Edit CMOS NAND gate must be compared and contrasted to the performance
characteristics of a commercially available NAND gate (specifically Fairchild’s CD4011BC
NAND gate). Since EE325 labs 3, 4, and 5 placed a heavily emphasis on the use and
performance of L-Edit, and PSpice as a circuit simulation tool, the intended audience of this
report should already be knowledgeable in the use of L-Edit and PSpice and the methods
used in finding the L-Edit NAND gate models characteristics. Thus the detailed procedures
that were offered in previous reports have been omitted from this report, although the
general simulation and circuit diagrams that were used are still included to allow a quick
visual guidance for further attempts at reconstructing this lab.
Requirements and Design Approaches / Trade-offs
The requirements for this lab are to design a two-input NAND gate with appropriate sizes
necessary for handling a total propagation delay of less than 50 ns, while carrying a 10 pF
load capacitance in PSpice. The design must use the MORBN20 design rules, and use the
default 2 micron, N-Well, double-metal, 11-mask CMOS SCNA technology design
constraints. After the design pFET and nFET constraints are determined and the model is
built in L-Edit a design rule check must be completed with zero DRC errors. Finally the
device must be extracted for use in PSpice and compared/contrasted against Fairchild’s
CD4011BC NAND gate with a matching load resistance and capacitance. The final
benchmarks should compare logic thresholds, noise margins, and propagation delays of the
L-Edit modeled CMOS NAND gate against the Fairchild CD4011BC NAND gate, and show
that the above design constraints are met.
3

4. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
L-Edit CMOS NAND Gate Design Details
In order to achieve the design specifications required by this lab the following
procedures/calculations were made in order to determine the required width and lengths
of the L-Edit CMOS NAND gate pFET and nFET devices. The design approach and
calculations follow as illustrated by figures 1 and 2.
Figure 1: Hand drawn model of CMOS NAND gate and lab design objectives. It was determined that
device resistances must be less than 1 kΩ, which provided a max channel current of 5 mA.
4

5. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Figure 2: Hand Calculations used to determine the L-Edit pFET and nFET devices widths and lengths.
L-Edit CMOS NAND Gate Layout
With the results from the hand calculations the design phase began using the CMOS NAND
gate model provided by page 5-9 of the 1995 book titled, “Physical Design of CMOS
Integrated Circuits Using L-Edit” by John P. Uyemura.
Figure 3: L-Edit CMOS NAND gate design. The left side is the two pFETs (In parallel), the right side is
the two nFETs (In series). Notice the pFETs device widths are approximately 3 times the nFETs.
5

6. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
L-Edit CMOS NAND Gate Cross Sections
Obtaining the CMOS NAND Gates cross section was accomplished by clicking Tools/Cross-
Section and clicking on the CMOS NAND Gate PMOS and NMOS sections by using the “Pick”
button.
Figure 4: L-Edit CMOS NAND Gate NMOS Cross Section.
Figure 5: EE325 L-Edit CMOS NAND Gate PMOS Cross Section.
L-Edit CMOS NAND Gate Design Rule Check Results
-------------------- NAND_DRC.DRC ---------------------
DRC Errors in cell Cell0 of file G:CMOS STUFF LAB 6LAB6.
0 errors.
DRC Merge/Gen Layers Elapsed Time: 0.000000 seconds.
DRC Test Elapsed Time: 0.000000 seconds.
DRC Elapsed Time: 0 seconds.
-------------------------------------------------------
6

7. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
L-Edit CMOS NAND Gate Extracted File
Some important things to not about this file, are the “Node Name Aliases”, these are the net
aliases names that must be used in PSpice. Also mentioned are PMOS and NMOS lengths
and widths. Note that the PMOS width must be about 2.8 times the NMOS width.
-------------------- NAND.SPC ---------------------
* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;
* TDB File: G:CMOS STUFF LAB 6LAB6, Cell: Cell0
* Extract Definition File: C:LEditmosismorbn20.ext
* Extract Date and Time: 06/02/2010 - 15:00
* WARNING: Layers with Unassigned AREA Capacitance.
* <Poly Resistor>
* <Poly2 Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* WARNING: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <Poly2 Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* <Poly1-Poly2 Capacitor>
* WARNING: Layers with Zero Resistance.
* <Pad Comment>
* <Poly1-Poly2 Capacitor>
* <NMOS Capacitor>
* <PMOS Capacitor>
* NODE NAME ALIASES
* 1 = Vout (17.5,35.5)
* 2 = VA (23.5,-8.5)
* 3 = VDD (-65.5,17.5)
* 4 = GND (67.5,-2.5)
* 5 = VB (32.5,-8.5)
M1 VDD VB Vout VDD PMOS L=2u W=70u AD=1.05n PD=310u AS=560p PS=156u
* M1 DRAIN GATE SOURCE BULK (-57.5 8.5 12.5 10.5)
M2 Vout VA VDD VDD PMOS L=2u W=70u AD=560p PD=156u AS=1.05n PS=310u
* M2 DRAIN GATE SOURCE BULK (-57.5 18.5 12.5 20.5)
M3 GND VB 6 GND NMOS L=2u W=23u AD=161p PD=60u AS=184p PS=62u
* M3 DRAIN GATE SOURCE BULK (42.5 8.5 65.5 10.5)
M4 6 VA Vout GND NMOS L=2u W=23u AD=184p PD=62u AS=184p PS=62u
* M4 DRAIN GATE SOURCE BULK (42.5 18.5 65.5 20.5)
* Total Nodes: 6
* Total Elements: 6
* Extract Elapsed Time: 0 seconds
.END
-------------------------------------------------------
7

8. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Edited SCNA.CSE File Required for using L-Edit CMOS NAND Gate
Lines 2 and 11 of this file were edited to change CMOSN to NMOS and CMOSP to PMOS.
-------------------- SCNA.SPC ---------------------
* THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS
.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10
+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172
+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000
+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03
+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000
+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10
+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is -0.25 um
.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10
+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715
+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9
+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02
+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000
+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10
+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is -1.14 um
--------------------------------------------------------
CMOS NAND Gate Test Plan
Now that the L-Edit CMOS NAND gate device has been created, passed its DRC, and
extracted. The next phase is to import the design files as accomplished previously in lab 5,
to test the device constraints in PSpice. However, first we must have a good commercially
available NAND gate to compare our L-Edit NAND gate to. Next, the characteristics of the
commercial NAND gate must be compared against the L-Edit model to include logic
thresholds, noise margins, and propagation delays. Conclusions will be based upon how
well our design first accomplishes our original goal (total propagation delay < 50 ns), and
how well our L-Edit NAND gate competes against the commercial NAND gate.
8

9. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Fairchild Semiconductor
CD4011BC Quad 2-Input NAND Buffered B Series Gate Characteristics
The commercial NAND gate chosen for comparison against our L-Edit NAND gate was
Fairchild’s CD4011BC Quad 2 input buffered NAND gate. This is a low power, TTL,
monolithic complementary MOS (CMOS) NAND gate constructed with n-channel and p-
channel enhancement mode transistors with equal source and sink current capabilities,
and symmetric output characteristics. Fairchild’s CD4011BC NAND gate further features
buffered outputs which improve the devices characteristics by providing a very high gain.
The datasheet used for comparing this NAND gate against our L-Edit gate can be
downloaded from: http://www.fairchildsemi.com/ds/CD/CD4001BC.pdf.
Figure 6: Fairchild CD4011BC Quad 2 Input NAND Gate DC Electrical Characteristics.
Figure 7: Fairchild CD4011BC Quad 2 Input NAND Gate AC Electrical Characteristics.
9

10. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
CD4011BC
Characteristic
Parameter Ideal NAND Gate
Procedure
+25˚ C
Transfer Char. Vthreshold 2.5 V 2.5
Minimum HIGH input voltage VIH 2.5 3.5
Maximum LOW input voltage VIL 2.5 1.5
Minimum HIGH output voltage VOH 5 4.95
Maximum LOW output voltage VOL 0 0.05
Noise NMH = VOH -VIH 2.5 V 1.45 V
Margins NML = VIL - VOL 2.5 V 1.45 V
Typ: 90ns
Rise Time tLH 0s
Max: 200ns
Typ: 90ns
Fall Time tHL 0s
Max: 200ns
Typ: 120ns
tPHL 0s
Max: 250ns
Typ: 85ns
tPLH 0s
Propagation Delays Max: 250ns
tP = Typ: 106.5ns
0s
.5 * (tPHL + tPLH) Max: 250ns
Table 1: CD4011BC NAND Gate quick reference table for Lab 6.
10

11. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Voltage Transfer Function for the CMOS NAND Gate Circuit
Using the same approach that was used in labs 3, 4, and 5 our first step in comparing our L-
Edit NAND gate design against the CD4011BC NAND gate is to verify the Voltage Transfer
Function (Logic Threshold, and Noise Margins) of our NAND gate. To accomplish this the
circuit shown by figure 8 was built and simulation settings were set as illustrated by
figures 9 and 10. First the logic threshold for input B was taken by sweeping input B, next
the logic threshold, and circuit noise margins were calculated against by sweeping input A.
Results are shown in figures 11 and 12.
0 0
VA VB
5Vdc 5Vdc
VA VB
VDD L-Edit CMOS NAND Gate R1
0
VDD P-CH W/L = 70/2 um GND
0
5Vdc
N-CH W/L = 23/2 um 1
Vout
V
RL
200k
CL
50pF
0
Circuit used for generating the L-Edit CMOS NAND Gate
Voltage Transfer Characteristics.
Figure 8: PSpice circuit for generating the L-Edit CMOS NAND Gate voltage transfer function (Vout vs.
Vin).
Figure 9: Simulation Settings (DC Sweep) used for obtaining the voltage transfer function.
11

12. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Figure 10: Configuration files needed to correctly run simulation of L-Edit NAND gate in PSpice.
5.0V
V
o Logic Threshold for Input B
l
t
a
g
e
2.5V (2.4917,2.4917)
Logic Threshold / Switching Point
0V
0V 1.0V 2.0V 3.0V 4.0V 5.0V
V(VOUT) V_VB/1
V_VB
Figure 11: Logic threshold graph for Input B.
12

13. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
0
S
l
o
p (2.2918,-1.0000) (3.1167,-1.0000)
e Slope = -1 Slope = -1
-10
-20
-30
D(V(Vout))
5.0V
V
o
l
t (2.2918,4.4912)
a
VIL, VOH
g
e Noise Margins and Logic Threshold
For Input A
2.5V
NML = 1.827443 V
NMH = 1.3745 V (2.6238,2.6238)
Logic Threshold / Switching Point
VIH, VOL
(3.1167,464.357m)
SEL>>
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(VOUT) V_VA/1
V_VA
Figure 12: Logic Threshold and Noise Margins for input A. Results are in table below.
CMOS
Winner
Noise Margin Comparison Ideal CD4011BC NAND Gate
% error
Parameter NAND Gate NAND Gate Input A
(vs. Ideal)
unless noted
Input A: 2.6238 V
Logic Threshold or Switching Point 2.5 V 2.5 V CD4011BC
Input B: 2.4917 V
VIH = minimum HIGH input voltage 2.5 V 3.5 V 3.1167 V L-EDIT NAND
VIL = maximum LOW input voltage 2.5 V 1.5 V 2.2918 V L-EDIT NAND
VOH = minimum HIGH output voltage 5V 4.95 V 4.4912 V CD4011BC
VOL = maximum LOW output voltage 0V .05 V 464.357 mV L-EDIT NAND
Noise Margin Low = NML = VIL – VOL 2.5 V 1.45 V 1.827443 V L-EDIT NAND
Noise Margin High = NMH = VOH – VIH 2.5 V 1.45 V 1.3745 V CD4011BC
Table 2: L-Edit NMOS Noise Margin Comparison Table, all percentages are rounded.
From these results it can be seen that that our nFET and pFET devices have different logic
thresholds. This is due to the different operating characteristics and current mobility of the
n and p channel devices. The noise margins define how well the NAND gates withstand
electrical noise. The results show that our L-Edit NAND has a better NM L than the
CD4011BC NAND but a worse NMH.
13

14. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
0 0
V1 = 0 V1 = 0
V2 = 5 VA VB V2 = 5
TD = 0 TD = 0
TR = 10ps TR = 10ps
TF = 10ps TF = 10ps
PW = 100ns PW = 50ns
PER = 200ns
PER = 100ns
V V
VA VB
VDD L-Edit CMOS NAND Gate R1
0
VDD P-CH W/L = 70/2 um GND
0
5Vdc
N-CH W/L = 23/2 um 1
Vout
V
RL
200k
CL
50pF
0
Circuit used for verifing the L-Edit CMOS NAND Gate
truth table. VA pulse = 5MHz, VB pusle = 10MHz
Figure 13: PSpice circuit for verifying the L-Edit CMOS NAND Gate truth table.
The PSpice circuit was again modified as illustrated by figure 13, to allow us to perform a
truth table verification of our NAND gate circuit. This was accomplished by setting up
input A as a 5 MHz pulse (PER = 200ns) and input B as a 10 MHz pulse (PER = 100ns), both
inputs pulsing from 0V to 5V.
Figure 14: Simulation Settings for verifying L-Edit NAND gate truth table.
14

15. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
The results from the simulation are shown in figure 15 below. From the results our L-Edit
NAND gate is working as expected and only outputting 0V (low) when both inputs A and B
are 5V (high). Otherwise “Vout” is 5V (high).
5.5V
V
Sim results for verifying truth table VA = 5MHz pulse (0-5V), VB = 10MHz pulse (0-5V)
o
l
t
VA = 5V VA = 5V VB = 5V Vout = 1V
a
VB = 5V Vout = 1V Vout = 1V
g
e
4.0V
2.0V
Notice: Vout only = 0V when
VA = 5V, and VB = 5V
Both Inputs are logic 1
VA = 0V
VB = 0V
Vout = 0V VB = 0V VA = 0V
0V
0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns
V(VOUT) V(VA) V(VB)
Time
Figure 15: PSpice simulation results for truth table verification.
15

16. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
L-Edit CMOS NAND
Truth Table
Input Output
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0
Table 3: Truth table for the L-Edit CMOS NAND Gate.
The results from figure 15 and table 3 have successfully shown that our L-Edit NAND gate
is performing as a NAND gate should. Next PSpice circuit and simulation settings will be
adjusted to verify that our circuit is meeting our original design specifications (propagation
delay < 10 ns) and finally our NAND gate will be compared against the commercial NAND
gate.
16

17. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Propagation Delays of the CMOS NAND Gate Circuit
The rise/fall times and propagation delay times of our L-Edit NAND gate will be measured
as was accomplished similarly in labs 3, 4, and 5. Two circuit designs were used, the first
(figure 16) was used to find the propagation delay against a capacitive load of 10 pF (our
original design specification), and the second (figure 17) was used to find the propagation
delay against a capacitive load of 50 pF (for accurate comparison against Fairchild’s
CD4011BC NAND gate). Input A was setup as a 7.5 MHz pulse as requested by the
instructor (use a frequency between 5MHz and 10MHz).
0 0
V1 = 0
V2 = 5 VA
TD = 0
TR = 10ps VB
TF = 10ps 5Vdc
PW = 66.666ns
PER = 133.333ns
VA VB
VDD L-Edit CMOS NAND Gate R1
0
VDD P-CH W/L = 70/2 um GND
0
5Vdc
N-CH W/L = 23/2 um 1
Vout
V
RL
200k
CL
10pF
0
Circuit used for verifing the L-Edit CMOS NAND Gate
propogation delays at VA freq = 7.5MHz, CL = 10pF
Figure 16: PSpice circuit for finding the L-Edit CMOS NAND Gate circuits propagation delays and
digital frequency response at frequency 7.5MHz with 10pF load capacitance (CL).
0 0
V1 = 0
V2 = 5 VA
TD = 0
TR = 10ps VB
TF = 10ps 5Vdc
PW = 66.666ns
PER = 133.333ns
VA VB
VDD L-Edit CMOS NAND Gate R1
0
VDD P-CH W/L = 70/2 um GND
0
5Vdc
N-CH W/L = 23/2 um 1
Vout
V
RL
200k
CL
50pF
0
Circuit used for verifing the L-Edit CMOS NAND Gate
propogation delays at VA freq = 7.5MHz, CL = 50pF
Figure 17: PSpice circuit for finding the L-Edit CMOS NAND Gate circuits propagation delays and
digital frequency response at frequency 7.5MHz with 50pF load capacitance (CL).
17

18. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Figure 18: PSpice simulation setting used to find propagation delay times of 7.5MHz input.
5.5V
V
Propogation Delays for VA pulse = 7.5MHz with 10pF load capacitance
o
l
t
a (203.036n,4.9992) (266.818n,5.0060)
g
e
(200.601n,4.5000) (266.928n,4.5000)
4.0V
tLH (rise) is from .1 Vdd to .9 Vdd
tHL (fall) is from .9 Vdd to .1 Vdd
pHL is time to (rise) from 0 to 2.5V
pLH is time to (fall) from 5 to 2.5V
(200.228n,2.5000) (267.256n,2.5000)
2.0V tLH (rise) = 515 ps
tHL (fall) = 813 ps
pLH = 438 ps
pHL = 170 ps
tp = 304 ps
(200.086n,500.000m) (267.741n,500.000m)
0V (200.058n,18.072m) (269.294n,18.072m)
195ns 200ns 210ns 220ns 230ns 240ns 250ns 260ns 270ns 275ns
V(VOUT)
Time
Figure 19: PSpice simulation results of circuit with 10pF load. Circuit correctly meets design
specifications with all rise/fall times and propagation delays less than 10 ns.
18

19. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
From the results obtained by figure 19 above our L-Edit CMOS NAND gate’s total
propagation delay of 304 ps is well below our original requirement of a total propagation
delay less than 50 ns using a load capacitance of 10pF. After adjusting the circuit load
capacitance to 50 pF to match the Fairchild CD4011BC NAND gate load capacitance our
final simulation was ran for a final apples to apples comparison between NAND gates.
5.5V
V
o Prop delays for VA pulse = 7.5MHz with a 50pF load capacitance
l
t
a (203.036n,4.9998)
tLH is the time to (rise) from .1Vdd to .9Vdd (266.818n,5.0060)
g
e tHL is the time to (fall) from .9Vdd to .1Vdd
(200.601n,4.5000) pHL is the time to (rise) from 0 to 2.5V (266.928n,4.5000)
4.0V pLH is the time to (fall) from 5 to 2.5V
Comparison
L-Edit CMOS NAND Gate CD4011BC NAND Gate
tLH = 515 ps tLH = 90 ns
(200.228n,2.5000) (267.257n,2.5000)
tHL = 814 ps tHL = 90 ns
pHL = 171 ps pHL = 120 ns
2.0V pLH = 439 ps pLH = 85 ns
tp = 305 ps tp = 106.5 ns
(200.086n,500.000m) (267.742n,500.000m)
0V (200.057n,6.0241m) (269.465n,18.072m)
195ns 200ns 210ns 220ns 230ns 240ns 250ns 260ns 270ns 275ns
V(VOUT)
Time
Figure 20: PSpice simulation results of circuit with 50pF load. The L-Edit CMOS NAND gate clearly out
performs the Fairchild CD4011BC NAND gate. Table 4 contrasts these results.
From the results obtained by figure 20 above we can calculate the following (table 4)..
Note a small %error in tPHL and tPLH may be the parasitic capacitance and resistance of the
CMOS NAND Gate.
19

20. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
L-Edit CMOS
CD4011BC
Parameter Ideal NAND Gate Winner
NAND Gate (CL = 50 pF)
L-Edit
tHL = the time it takes output voltage to drop from 4.5 V to .5 V 0s 90 ns 814 ps
NAND
L-Edit
tLH = the time it takes output voltage to rise from .5 V to 4.5 V 0s 90 ns 515 ps
NAND
L-Edit
tPLH = the time it takes output voltage to rise from 0 to 2.5 V 0s 85 ns 439 ps
NAND
L-Edit
tPHL = the time it takes output voltage to fall from 5 V to 2.5 V 0s 120 ns 171 ps
NAND
L-Edit
tP = Propagation delay time = .5 * ( tPLH + tPHL ) 0s 106.5 ns 305 ps
NAND
Max Switching Frequency (calculated) = 1/( tLH + tHL ) L-Edit
∞ 5.55 MHz 752 MHz
*Note: Calculated result is usually far off from actual result. NAND
Table 4: CMOS NAND Gate Rise/Fall times and Propagation Delay Comparisons.
Clearly our L-Edit NAND gate is capable of switching much faster than the Fairchild
CD4011BC NAND gate due to the shorter propagation delays and rise/fall times making it a
clearer choice for higher frequency applications.
L-Edit CMOS
Winner
Evaluation Ideal CD4011BC NAND
Parameter % error
Procedure NAND NAND Input A, unless
(vs. Ideal)
noted.
Input A: 2.6238 V
Transfer Char. VThreshold 2.5 V 2.5 V CD4011BC
Input B: 2.4917 V
Noise NMH 2.5 V 1.45 V 1.3745 V CD4011BC
Margins NML 2.5 V 1.45 V 1.827443 V L-Edit NAND
Rise Time tLH 0s 90 ns 515 ps L-Edit NAND
Fall Time tHL 0s 90 ns 814 ps L-Edit NAND
tPHL 0s 120 ns 171 ps L-Edit NAND
Propagation Delays tPLH 0s 85 ns 439 ps L-Edit NAND
tP 0s 106.5 ns 305 ps L-Edit NAND
Table 5: Summary of results for Lab 6.
20

21. EE325, CMOS Design, Lab 6: L-Edit CMOS NAND Gate
Conclusion and Recommendations
The L-Edit CMOS NAND gate clearly met all device specifications and delay requirements as
demonstrated by this report and table 5. Furthermore, the L-Edit CMOS NAND gate offers
superior frequency response in comparison to the Fairchild’s CD4011BC Quad 2 input
buffered NAND gate. This makes the L-Edit NAND gate a competitive gate for higher
frequency applications. The logic threshold and noise margin results showed that the
Fairchild NAND gate operated very close to our L-Edit designed NAND gate with a better
high noise margin and logic threshold but a worse low noise margin. However, due to the
slow switching speed of the Fairchild CD4011BC NAND gate our L-Edit design would still
make a good design alternative, especially for higher frequency applications.
This was an excellent lab at demonstrating the powerful versatility offered through custom
design modeling of CMOS logic gates using L-Edit, and showed that alternative CMOS
designs can sometimes perform better than commercial alternatives.
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