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Naveen Chinnasamy

Presented by,
Naveen C
M.E. VLSI DESIGN
SONA COLLEGE OF TECHNOLOGY
SALEM
AN EFFICIENT PIPELINED
FEEDFORWARD-FFT ARCHITECTURE
USING SPLIT RADIX

 To reduce the number of adders and multipliers
in FFT.
 To increase the speed by reducing time delay
between consecutive inputs using pipelining.
OBJECTIVE

ABSTRACT
Generally FFT has complex operations which
needs more computational time. Complex operations
can be reduced by using split radix algorithm. Split
radix FFT has been designed with Feedforward
pipelining architecture and this can reduce the delay
between the consecutive inputs, and speed of
computation can been increased.

Radix 2 Butterfly structure
RADIX 2 BUTTERFLY STRUCTURE

EXISTING FLOW DIAGRAM
16 POINT RADIX 2 ALGORITHM

 Split radix algorithm will use the advantages of both
radix 2 and radix 4 algorithm.
 Split radix have in-place property.
 It have its own butterfly structure.
PROPOSED ALGORITHM

SPLIT RADIX BUTTERFLY STRUCTURE
BASIC SPLIT RADIX ALGORITHM

PROPSED FLOW DIAGRAM
16 POINT SPLIT RADIX ALGORITHM

TOOLS REQUIRED
 Modelsim 5.7g
COMPARISON
• Split Radix FFT computation time.

CONCLUSION
• The paper shows the use of Split-radix FFT
with feedforward pipelining (MDC).
• The SRFFT decreases the number of addition
and complex operations. Due to pipelining the
time latency is been reduced and by increasing
the number of parallel samples, throughput of
the design is increased.
• Thus this design provides efficient results in
performance using SRFFT.

REFERENCE
1. Garrido. M.,Grajal. J.,“Pipelined Radix 2K
Feedforward FFT
Architectures”, IEEE Trans. vol. 21, no. 1, January 2013.
2. Duhamel. P, “Implementation of "Split-radix" FFT algorithms
for complex, real, and real-symmetric data,” IEEE trans. vol.
assp-34. no. 2, april 1986.
3. J. W. Cooley and J. W. Tukey, “An algorithm for machine
computation of complex Fourier series,” Math Comput., vol. 19,
pp. 297- 301, 1965.
4. E. H. Wold and A. M. Despain, “Pipeline and parallel-
pipeline FFT processors for VLSI implementations,” IEEE
Trans. Comput., vol. C-33, no. 5, pp. 414–426, May 1984.

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NaveeN

1. Presented by, Naveen C M.E. VLSI DESIGN SONA COLLEGE OF TECHNOLOGY SALEM AN EFFICIENT PIPELINED FEEDFORWARD-FFT ARCHITECTURE USING SPLIT RADIX

2.  To reduce the number of adders and multipliers in FFT.  To increase the speed by reducing time delay between consecutive inputs using pipelining. OBJECTIVE

3. ABSTRACT Generally FFT has complex operations which needs more computational time. Complex operations can be reduced by using split radix algorithm. Split radix FFT has been designed with Feedforward pipelining architecture and this can reduce the delay between the consecutive inputs, and speed of computation can been increased.

4. Radix 2 Butterfly structure RADIX 2 BUTTERFLY STRUCTURE

5. EXISTING FLOW DIAGRAM 16 POINT RADIX 2 ALGORITHM

6.  Split radix algorithm will use the advantages of both radix 2 and radix 4 algorithm.  Split radix have in-place property.  It have its own butterfly structure. PROPOSED ALGORITHM

7. SPLIT RADIX BUTTERFLY STRUCTURE BASIC SPLIT RADIX ALGORITHM

8. PROPSED FLOW DIAGRAM 16 POINT SPLIT RADIX ALGORITHM

9. BLOCK DIAGRAM

10. RESULT : INPUT

11. OUTPUT WITH PIPELINING

12. OUTPUT WITHOUT PIPELINING

13. TOOLS REQUIRED  Modelsim 5.7g COMPARISON • Split Radix FFT computation time.

14. CONCLUSION • The paper shows the use of Split-radix FFT with feedforward pipelining (MDC). • The SRFFT decreases the number of addition and complex operations. Due to pipelining the time latency is been reduced and by increasing the number of parallel samples, throughput of the design is increased. • Thus this design provides efficient results in performance using SRFFT.

15. REFERENCE 1. Garrido. M.,Grajal. J.,“Pipelined Radix 2K Feedforward FFT Architectures”, IEEE Trans. vol. 21, no. 1, January 2013. 2. Duhamel. P, “Implementation of "Split-radix" FFT algorithms for complex, real, and real-symmetric data,” IEEE trans. vol. assp-34. no. 2, april 1986. 3. J. W. Cooley and J. W. Tukey, “An algorithm for machine computation of complex Fourier series,” Math Comput., vol. 19, pp. 297- 301, 1965. 4. E. H. Wold and A. M. Despain, “Pipeline and parallel- pipeline FFT processors for VLSI implementations,” IEEE Trans. Comput., vol. C-33, no. 5, pp. 414–426, May 1984.

16. THANK YOU

NaveeN

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