THRIS (Telecom Hardware Robustness Inspection System) is an automatic qualification and test environment developed in co-operation by CSELT, the central research laboratory of the STET group in the telecommunication field, HP and HDT under commitment of Telecom Italia. THRIS is a new conception tool focused on the most critical issues affecting the quality of telecom hardware, well suited for both operating companies and manufactures. It can be utilised with great benefits and cost savings through the entire life of a telecom product from the early design stage up to field operation.

1. 1 Piero Belforte 1997
Telecom Hardware Robustness
Inspection System
Number of Visitor of THRIS Home Page since 08/04/97:
THRIS (Telecom Hardware Robustness Inspection System) is an automatic qualification
and test environment developed in co-operation by CSELT, the central research
laboratory of the STET group in the telecommunication field, HP and HDT under
commitment of Telecom Italia.
THRIS is a new conception tool focused on the most critical issues affecting the quality
of telecom hardware, well suited for both operating companies and manufactures. It can
be utilised with great benefits and cost savings through the entire life of a telecom
product from the early design stage up to field operation.
Today hardware quality is more and more affected by malfunctions
due to the increase of complexity and speed of the integrated
circuits, the introduction of high-density packaging technologies,
electromagnetic compatibility (EMC) problems and to the more
demanding performance limits of new telecom systems. Even the
response of the system to faults and its diagnostic coverage are
becoming more and more difficult to evaluate. Telecom manufactures have to face these
emerging problems with critical time-to-market and cost constraints while operating
companies need to evaluate the intrinsic quality of the systems they are going to buy.
THRIS has been conceived to solve these problems, locating the hidden causes of
malfunctions even before the prototype is available, performing a true quality evaluation
based only on design data. If the prototype is available, THRIS allows the user to inject
controlled faults and perturbations inside the system, in order to evaluate its actual
operating margins and its overall behaviour in faulty conditions.

2. 2 Piero Belforte 1997
Monitoring of the system internal functioning is the third main feature integrated in
THRIS to detect the real cause of system failures and malfunctions even in actual field
operation.
Major Benefits
For the Telecom Operating Companies:
 Evaluation of hardware robustness and operating margins inside the system.
 EMC evaluation of new products.
 Reliability evaluation.
 Controlled fault insertion for qualification trials.
 Automated procedure for hw/sw regression testing related to fault tolerance and diagnostic
performance.
 System observation through monitoring of critical hardware parameters during both
qualification and operation phases.
For the Manufacturers:
 Reduction of design recycles and improvements of time-to-market.
 Early detection of critical areas before prototyping.
 EMC prediction before compliance test.
 Early reliability evaluation.
 Monitoring of system prototype malfunctions and hardware operating margins.
 Automated procedure for hw/sw integration trials and regression testing through automated
fault insertion.
 System dependability validation.
 Tool and methodology shared with the telecom operators.
Hardware Robustness Analysis by Simulation
Signal Integrity analysis can be performed on hardware modules
(typically printed circuit boards) by means of the post-layout
tool PRESTO TM
embedded in the THRIS environment.
A large number of tests can be executed on a simulative model
automatically extracted from manufacturer's CAD data. These tests
can pinpoint problems related to component stress, signal
degradation, interference due to crosstalks between traces, and switching noise on power
and ground distribution. Signals not respecting user specifications are easily identified.
Accurate electrical models of components can be obtained from an experimental setup
including a TDR (Time Domain Reflectometer) linked to THRIS.

3. 3 Piero Belforte 1997
EMC Behaviour Prediction by Simulation
Telecom products, like any other electronic equipment, must
comply to specific EMC international stardards. The corrective
actions on products that do not satisfy EMC requirements can be
extremely costly for manufacturers and can create time-to-market
problems for telecom operators. THRIS software is able to predict
the EMC behaviour of electronic modules during the design phase.
Starting from p.c.b. CAD data it is possible to simulate the emission profiles that would
be obtained from the experimental tests and compare them to the emission levels
allowed by the standards. In this way, the most critical signals from EMC point of view
can be detected and corrective actions can be taken before prototype implementation
with great savings of time and costs.
Fault/Noise Insertion on the Simulated System
Fault insertion is necessary during qualification trials to evaluate
overall system behaviour in faulty conditions. THRIS automatic
procedures utilise the simulative model of hardware modules to
predict the spurious effects due to the physical connection of fault
actuators and insure the effectiveness and repeatibility of fault
insertion tests that will be carried out on the physical system.
Simulative tests can evaluate both normal and faulty operations of
an apparatus consisting of several hardware modules connected
together. A great variety of digital streams can be applied as stimuli
to the system under test to simulate real traffic conditions and the
results can be displayed in terms of eye-diagrams and compared
with user-defined or standard signal masks. In the case shown,
regarding a STM1 apparatus, internal signal degradation can become a major cause of
system malfunctions even if the functional test results are correct.
Telecom Hardware Robustness Inspection System
Fault/Noise Insertion on the Physical System
THRIS hardware front-end includes miniaturised fault insertion
probes that can be connected to the system under test without
particular design requirements and no need of extender cards.
Fault actuators, noise injectors and passive monitoring probes can
be inserted in any type of electronic module and the connection

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point of each probe is optimized by the software in order to limit spurious effects within
user specified limits. Probe mounting procedure and cable assignment are fully driven
and documented by THRIS software.
The status of fault and noise injection probes is electronically controlled allowing
repetitive tests, without permanent damage of components.
The boards equipped with THRIS probes can be archived for regression trials.
Fault Actuation and System Monitoring through VEE User
Interface
THRIS console allows the operator to activate fault insertion and
signal monitoring functions.
The user selects the module under test and the specific signal where
the fault has to be applied. In a similar way it is possible to select
the signal to be monitored during normal operation or when the
fault is applied.
Thanks to the VEE environment, the user interface is very friendly and can be easily
customized to cover new test applications.
Integration within other proprietary test environments is also possible.
Future Evolutions
THRIS is mainly an evolutive project that will cover in the near
future more and more applications with the aim of becoming a
standard methodology used by Manufacturers and Telecom
Operators.
The TUG (THRIS User Group) initiative recently promoted by
CSELT and sponsored by Telecom Italia is already operative to
address the future releases of the tool by taking into account the
needs of its partecipants.
TUG interests include predictive EMC to increase the success probability of final
compliance tests of new products.
A great emphasis will be given to the extension of THRIS simulation capabilities and to
the tool validation through extensive experimental tests.
Other add-on options of THRIS will cover high-speed applications like SDH apparatus,
enhanced component modelling capabilities and early reliability evaluations of
electronic modules based on a specific CSELT/Telecom Italia methodology.

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THRIS Basic Configuration
Hardware
HP9000/745
E1401A
E1406A
E1458A
E1366A + E1403B
E1428A
E1445A
C2145A
UNIX Workstation and system controller
C-size VXI Mainframe
Command module
96-channel digital I/O *
50 ohm RF Mux (2x4:1) **
1 Gsample/s 2-channel digitizing oscilloscope
Arbitrary function generator
Desk jet colour printer
Software
E2111B
-
PRESTO
EmiR
-
Visual Engineering Environment
VXI Instrument & probe control software ***
Post-layout analysis environment, including THRIS facilities for fault insertion and test
documentation
Radiated emission prediction tool
SW link between VEE and PRESTO environments
Optional
54120A
54750A
8590EM
Time-Domain Reflectometer for component characterisation
(sw link to PRESTO)
High bandwidth digitizing oscilloscope and TDR
EMC precompliance analyser
* Additional modules can be used to expand the number of fault insertion points.
** Additional modules can be used to expand the number of monitoring/noise injection
channels.
*** Customisable for specific test applications.
THRIS is a trademark of CSELT.
PRESTO and EmiR are trademarks of HDT.

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Fault insertion & signal monitoring Front-End (patents pending):
Miniaturised fault actuators:
 compatible with through-hole and SMT technologies
 stuck-at-0 and stuck-at-1 for ECL, CMOS, TTL digital families
 low electrical loading in off condition
 fully characterised (behavioural model)
Miniaturised passive probes:
 monitoring of signals inside modules
 low electrical loading
 fully characterised (behavioural model)
Miniaturised noise injectors:
 injection of noise inside operating modules
 monitoring of injected noise
 low electrical loading when disabled
 fully characterised (behavioural model)
Optical decoupling & signal conditioning modules:
 avoid ground loops when testing large systems
Miscellaneous:
 connectors and cables

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To get more information
Contact persons
Piero BELFORTE
CSELT
via G. Reiss Romoli 274
10148 - Torino
phone: +39 11 228 6905
fax: +39 11 228 7003
Giuseppe MORELLI
Telecom Italia S.p.A.
DRE/IR-INC
via di Val Cannuta, 250
00166 - Roma
phone: +39 6 3688 5733
fax: +39 6 3688 5811
Luigi Bragagnini
CSSD- Hewlett-Packard S.p.A.
via G. Di Vittorio, 9
20063 - Cernusco sul Naviglio (Milano)
phone: +39 2 92124447
fax: +39 2 92141485
Pierpaolo MORETTI
Telecom Italia S.p.A.
DRE/IR-IAP
via di Val Cannuta, 250
00166 - Roma
phone: +39 6 3688 5634
fax: +39 6 3688 8631
Emmanuel LEROUX
HDT
C.so Trapani, 16
10139 - Torino
phone: +39 11 746104
fax: +39 11 748109

8. 8 Piero Belforte 1997
PRESTO
Post-layout Rapid Exhaustive Simulation and Test
of Operation
PRESTO
is a Signal Integrity (SI) and
ElectroMagnetic Compatibility (EMC)
analysis environment able to predict the
behavior of electronic designs before
prototype implementation. EMC prediction
is becoming more and more important due
to the application of regulatory norms, so
that the EMC behavior of a new design has
to be analyzed and
corrected before compliance tests are
carried on system prototype.
PRESTO is the true solution to these
emerging problems allowing the designer to follow a step by step path to fix design
problems due to physical implementation.
PRESTO and its add-on modules (XTALKTM
, SSNTM
, EmiRTM
, EmiR-CableTM
,) predict in
an unique and fast way the effects of board layout on signal reflections, crosstalk,
switching noise and EMC issues due both to e.m. field radiation and conducted noise.
PRESTO usage increases the quality and
reliability of electronic designs, reducing
both the cost of design recycles and time to
market.
How PRESTO Works

9. 9 Piero Belforte 1997
PRESTO operation is based on layout data automatically extracted from the CAD
environment and then converted into an electrical network described as
a SPRINT
netlist where the routed traces are converted to transmission line models by
means of the embedded e.m. field solver PREFIS
.
Component models are automatically extracted from PRESTO component libraries.
Layout View
A specific layout window displays the nets
of the board under test. Problems due to
incorrect topologies can be easily
recognized inside PRESTO without the
need of other links with the CAD system.
Values of passive components can be easily
changed in order to perform a what-if
analysis on Signal Integrity (SI) and EMC
effects.
Model Libraries
Component models can be described
as SPRINT subcircuits in SPICE-like
syntax with no limitation in model
topology and complexity. Non standard
parts can be included automatically in the
netlist if previously defined as PRESTO special components. Wide-bandwidth models
can be developed by means of TDR (Time Domain Reflectometer) measurements on
actual components exploiting the facilities of the graphic environment SIGHTS
. This
feature is very important for high-speed and EMC applications.

10. 10 Piero Belforte 1997
Reports
An exhaustive compliance analysis on all
signals of the design with respect user-
defined masks can be performed and SI
reports can be obtained as mask violation
errors, in addition to the classic SI
parameters: transition times, overshoots,
delays, etc. Both graphical (SIGHTS) and
ASCII reports are available for both waveform analysis and fast screening of results.
The fast and accurate SI analysis is also the basis of a quick and accurate prediction of
radiated e.m. fields performed by PRESTO's EmiR module.
PLATFORMS
PRESTO runs on popular SUN SPARCstations and HP9000/700 series workstation
platforms.
Features Benefits
User friendly graphical interface Quick entry of both design data and test parameters
Modular add-on structure Step by step procedure to fix design problems
Powerful simulation engine (SPRINT)
Very fast checks of whole board
Avoid problems of net by net scan
Results match actual measurements
Unique solution for power/ground noise evaluation
Hierarchical model organization No model topologies limitation
Link to measurements
Accurate and reliable models, up to Gbit/s speed
Results validated in a broad range of applications
Wide range of test stimuli and checks Realistic tests to identify the causes of troubles