This document proposes a reduced latency list decoding algorithm and high throughput decoder architecture for polar codes. The reduced latency list decoding algorithm visits fewer nodes in the decoding tree and considers fewer possibilities of information bits than existing successive cancellation list decoding algorithms, significantly reducing decoding latency and improving throughput with little performance degradation. An implementation of the proposed decoder architecture in a 90nm CMOS technology demonstrates significant latency reduction and area efficiency improvement compared to other list polar decoders.

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A High Throughput List Decoder Architecture for Polar Codes
Abstract
While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless
channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error
performance of the SC algorithm is inferior for polar codes with finite block lengths. The cyclic
redundancy check (CRC)-aided SC list (SCL) decoding algorithm has better error performance
than the SC algorithm. However, current CRC-aided SCL decoders still suffer from long
decoding latency and limited throughput. In this paper, a reduced latency list decoding (RLLD)
algorithm for polar codes is proposed. Our RLLD algorithm performs the list decoding on a
binary tree, whose leaves correspond to the bits of a polar code. In existing SCL decoding
algorithms, all the nodes in the tree are traversed, and all possibilities of the information bits are
considered. Instead, our RLLD algorithm visits much fewer nodes in the tree and considers fewer
possibilities of the information bits. When configured properly, our RLLD algorithm
significantly reduces the decoding latency and, hence, improves throughput, while introducing
little performance degradation. Based on our RLLD algorithm, we also propose a high
throughput list decoder architecture, which is suitable for larger block lengths due to its scalable
partial sum computation unit. Our decoder architecture has been implemented for different block
lengths and list sizes using the TSMC 90-nm CMOS technology. The implementation results
demonstrate that our decoders achieve significant latency reduction and area efficiency
improvement compared with the other list polar decoders in the literature.
Tools :
 Xilinx 10.1
 Modelsim 6.4b
Languages :
 VHDL / Verilog HDL