Cell Technology for Graphics and Visualization

© 2002 IBM CorporationAugust 11, 2005
Cell Technology for Graphics and VisualizationCell Technology for Graphics and Visualization
Graphics Hardware Workshop 2005
Bruce D’Amora
Emerging Systems Software
IBM T.J. Watson Research Center
http://www.research.ibm.com

Cell Technology for Graphics and Visualization © 2005 IBM Corporation2
AgendaAgenda
Introduction
Architecture
Programming
Graphics & Visualization
Demos
Questions

IntroductionIntroduction

What is Cell?What is Cell?
Sony, Toshiba, IBM alliance established in March, 2001
− “STI” Design Center is located in Austin, Texas
Goals
− Outstanding performance, especially for game/multimedia
− Real time responsiveness to the user and the network
− Applicable to a wide range of platforms and applications
Design Concepts
− Compatibility with 64-bit Power Architecture™
− Increased efficiency and performance
− Non-homogeneous architecture

ArchitectureArchitecture

Cell Processor ArchitectureCell Processor Architecture
SPU
LS
SPU
LS
SPU
LS
SPU
LS
SPU
LS
SPU
LS
SPU
LS
EIB (up to 96B/cycle)
SPU
LS
16B/cycle
16B/cycle
SPE0 SPE1 SPE2 SPE3 SPE4 SPE5 SPE6 SPE7
L2
L1
PPU
32B/cycle
16B/cycle
MIC BIC
16B/cycle(2x)16B/cycle
Dual XDR™
I/O I/O
64-bit Power Architecture w/VMX
PPE
AUC
MFC MFC MFC MFC MFC MFC MFC MFC
AUC AUC AUC AUC AUC AUC AUC

Element Interconnect BusElement Interconnect Bus
EIB data ring for internal communication
− Four 16 byte data rings, supporting multiple transfers
− 96B/cycle peak bandwidth
− Over 100 outstanding requests

Power Processor ElementPower Processor Element
PPE handles operating system and control tasks
− 64-bit Power ArchitectureTM
with VMX
− In-order, 2-way hardware symmetrical multi-threading (SMT)
− Load/Store with 32KB I & D L1 and 512KB L2

Synergistic Processor ElementSynergistic Processor Element
SPE provides computational performance
− Dual issue, up to 16-way 128-bit SIMD
− Dedicated resources: 128 128-bit register file, 256KB Local Store
− Each can be dynamically configured to protect resources
− Dedicated DMA engine: Up to 16 outstanding requests per SPE

SPE HighlightsSPE Highlights
User-mode architecture
− No translation/protection within SPU
− DMA is full Power Architecture protect/x-late
RISC like structures
− 32 bit fixed instructions
− Clean design – unified Register file
VMX-like SIMD dataflow
− Broad set of operations (8 / 16 / 32 Byte)
− Graphics SP-Float
− IEEE DP-Float
Unified register file
− 128 entry x 128 bit
256KB Local Store
− Combined I & D
− 16B/cycle L/S bandwidth
− 128B/cycle DMA bandwidth
LS
LS
LS
LS
GPR
FXU ODD
FXU EVN
SFP
DP
CONTROL
CHANNEL
DMA SMM
ATO
SBI
RTB
BEB
FWD
14.5mm2 (90nm SOI)

I/O and Memory InterfacesI/O and Memory Interfaces
I/O Provides wide bandwidth
− Two configurable interfaces
− Up to 25.6 GB/s memory B/W
– Up to 70+ GB/s I/O B/W
– Practical ~ 50GB/s

ConfigurabilityConfigurability
Direct Attach XDR
Two I/O interfaces
– Configurable number of Bytes
– Coherent or I/O Protection
CELL
Processor
XDRtm XDRtm
IOIF0 IOIF1
CELL
Processor
XDRtm
XDRtm
IOIF BIF
CELL
Processor
XDRtm
XDRtm
IOIF
CELL
Processor
XDRtm
XDRtm
IOIF
BIF
CELL
Processor
XDRtm
XDRtm
IOIF
CELL
Processor
XDRtm
XDRtm
IOIF
BIF
CELL
Processor
XDRtm
XDRtm
IOIF
SW

ProgrammingProgramming

BE Features Exploited by SoftwareBE Features Exploited by Software
Keeping Intermediate/Control Data on-Chip
− MMU – SLBs, TLBs
− DMA from L2 cache-> LS
− LS to LS DMA
− Cache <-> Cache transfers (atomic update)
− SPE Signalling Registers
− SPE <-> PPE Mailboxes
Resource Reservation and Allocation
− PPE can be shared across logical partitions
− SPEs can be assigned to logical partitions
− SPEs independently or Group Allocated
PowerPC
(PPE)
L2 Cache
DMA with Intervention
Hardware Managed Cache Coherency
BE Chip
System Memory I/O
BIF/IOIF
MFC
Local Store
SPU
AUC
MFC
Local Store
SPU
AUC
MFC
Local Store
SPU
AUC
MFC
Local Store
SPU
AUC
MFC
Local Store
SPU
AUC
MFC
Local Store
SPU
AUC
Local Store to Local Store DMA
Atomic Update Cache

Models for Programming the CellModels for Programming the Cell
Function Offload
Application Specific Accelerators
Computation-Acceleration
Streaming
Shared Memory Multi-processor
Heterogeneous Thread Runtime Model
Single Source Compiler

Function OffloadFunction Offload
Easiest way to port applications to Cell
PPE can call procedure located on the SPE as if it were a
local PPE function
PPE and SPE use “stubs” as placeholders for local and
remote procedures
Main() image
f1() PPE stub
f2() image
f1() SPE stub
f1() image
PPE SPE

Function Offload via IDLFunction Offload via IDL
.idl file
IDL compiler
Program.c Function.cSPE_stub.cStub.hPPE_stub.c
SPE compiler
& linker
SPE binary
PPE compiler
linker
PPE binary
RPC run-time
library
IDL compiler facilitates the RPC
function offload
– Defines interfaces between
PPE main program and SPE
RPC program
Function loaded onto an SPE only once
− PPE can make multiple calls to that
procedure without having to reload it.

OS allocates and initializes SPE resources
N
N
N
N
N
N
N
Special Case: Application Specific AcceleratorsSpecial Case: Application Specific Accelerators
OS services invokes SPE function
System Memory
SPE Function
Graphics MPEGSSL
Vertex shaders
Encryption Decryption
Realtime
MPEG
Encoding
MPEG DecodeMPEG Decode
PPE
OS
Application
Services
PPE_mpeg_encode()
SPE_mpeg_encode()

Programming Models
Computational AccelerationComputational Acceleration
PowerPC
(PPE)
SPU Puts
Results
PPE
Puts
Initial Text
Static Data
Parameters System Memory
SPC Independently
Stages Text & Intermediate Data
Transfers while executing
PPE
SPU
Local Store
MFC
PPE
Gets
Results
PPE passes:
Text
Static Data
Parameters
SPU
executes
User created RPC libraries
− User acceleration routines
− User compiles SPE code
Local Data
− Data and Parameters passed in call
Global Data
− Data and Parameters passed in call
− Code manages global data
SPU
Local Store
MFC

Streaming ModelStreaming Model
SPE initiated DMA
Input/output/kernel streams
–DMA’d from system memory->LS or LS->LS
PPE
SPE1
Kernel()
SPE0
Kernel()
SPE7
Kernel()
XDR
In
.
I7
I6
I5
I4
I3
I2
I1
I0
On
.
O7
O6
O5
O4
O3
O2
O1
O0
…..
Data-parallel
PPE
SPE1
Kernel1()
SPE0
Kernel0()
SPE7
Kernel7()
XDR
In
.
.
I6
I5
I4
I3
I2
I1
I0
On
.
.
O6
O5
O4
O3
O2
O1
O0
…..
DMA DMA
Task-parallel
SPE7
Ki
SPE1
Ki
SPE0
Ki
XDR
In
.
I7
I6
I5
I4
I3
I2
I1
I0
…..
Data&Kernel Streams
Kn
.
.
K6
K5
K4
K3
K2
K1
K0
SPE7
Ki
PPE
On
.
O7
O6
O5
O4
O3
O2
O1
O0
SPE7
Ki

SharedShared--memory Multiprocessormemory Multiprocessor
The Cell Processor can be programmed as a shared-memory
multiprocessor, using two different instruction sets
The SPEs and the PPE fully inter-operate in a cache-coherent
Shared-Memory Multiprocessor Model
– All DMA operations in the SPEs are cache-coherent
– The DMA operations use an effective address that is common to all
PPE and SPEs
– Shared-memory store instructions are replaced by a store from the
register file to the LS, followed by a DMA operation from LS to shared
memory.
A compiler or interpreter could manage part of the LS as a local
cache for instructions and data obtained from shared memory.

Application Source
& Libraries
PPE object files SPE object files
SPESPE SPE SPE
Physical SPUs
SPESPE SPE SPE
Cell AwareOS ( Linux)
SPE Virtualization / Scheduling Layer (m->n spc threads)
New SPE tasks/threadsExisting PPE
tasks/threads
Physical PPE
PPE
MT1 MT2
PPE Threads, SPE Threads
Shared effective address space
SPE Virtualization in debug mode only
Heterogeneous MultiHeterogeneous Multi--Threading ModelThreading Model

Single source approach to programming Cell
Single Source Compiler
− Auto parallelization ( treat target Cell as an SMP )
− Auto SIMD-ization ( SIMD-vectorization )
− Compiler management of Local Store as 2nd level register file / SW managed cache (I&D)
− Most Cell unique piece
Optimization
− OpenMP pragmas
− Vector.org SIMD intrinsics
− Data/Code partitioning
− Streaming / pre-specifying code/data use
Prototype Single Source Compiler Developed in IBM Research

Graphics & VisualizationGraphics & Visualization

Graphics and Visualization on CellGraphics and Visualization on Cell
Terrain Rendering Engine
Multi-resolution Subdivision Surfaces
Geometry
Processing
Courtesy of Alias Systems
Cloth
Simulation

The Cell and GPUsThe Cell and GPUs
Extension to shader pipeline on GPUs
− Vertex shaders for geometric modeling
− NURBS
− Subdivision surfaces
− Continuous level of detail
− Vertex shaders for a additional lighting models
Physically Based Modeling
− Soft-body dynamics
− Rigid-body dynamics
Image Processing
− Background Subtraction for Video Surveillance
Global Illumination
– Raytracing
− Raycasting Terrains
− Rendering of DEMs
− Surface shaders for lighting, shadows

The Cell and GPUsThe Cell and GPUs
SPU
LS
MFC
SPE 6
PPU
L1
L2
PPE
SPU
LS
MFC
SPE 4
SPU
LS
MFC
SPE2
SPU
LS
MFC
SPE 0
SPU
LS
MFC
SPE 7
SPU
LS
MFC
SPE 5
SPU
LS
MFC
SPE3
SPU
LS
MFC
SPE 1
Physically-based modeling
• Soft/rigid body
• Fluid dynamics
Vertex Shaders
• Lighting models
• Subdivision
App
Cell
I/O&MemoryInterfaces
GPU
Pixel
Processing
Frame Buffer
Vertex
Processing
Local or network connection
Runtime generated
textures, maps,
vertices, etc.
Geometry, textures,
maps, etc.
AI
System
Memory
Terrain Generation
• Incl. depth maps
D
ata/code
flow
Control Meshes
Tesselated geom.
Maps, Textures, etc.

Image Processing on CellImage Processing on Cell
Video Surveillance
Background subtraction compares the current image (left) with a
reference image (middle) to find the changed regions (right)
corresponding to objects of interest.

BGS Application Structure
AGC & AWB
compensation
Kalman
smoothing
motion
energy
shadow &
highlights
pixel
differences
texture
differences
Image
Background
Mask
Salience
quiescent
area addition
slow update
blending
stationary
healing
determine
add / remove
statistical
thresholding
SIGNAL
contour
smoothing
component
pruning
per Jonathan Connell

Alternative 1Alternative 1 –– Single SPE for Video StreamSingle SPE for Video Stream
Each SPE dedicated to one or more video streams
Code overlaying may be needed to overcome the local memory
limitation
Seems most compatible with existing application structure
No code or data partitioning across SPEs
SPE 0
Video
Stream 1
SPE 1
Video
Stream 2
SPE 7
Video
Stream N

Alternative 2Alternative 2 –– Image Pipeline for TaskImage Pipeline for Task--levellevel
ParallelismParallelism
Functions are divided into groups
Groups set up in pipelined fashion
Each SPE dedicated to only one group
Outputs from one group passed SPE-to-SPE as inputs to the next
Code is partitioned – Data is not partitioned
Efficient utilization of SPEs
SPE 0
Video
Streams
SPE 1 SPE 7

Alternative 3Alternative 3 –– DataData--level Parallelismlevel Parallelism
For a given function, each SPE processes part of a frame
Not easily applied to all BGS functions
00 00 00 00 00 00 00 07
18 2D 43 5B 74 8D A2 B3
C5 D7 EC FF FF FF FF FF
FF FF FF FF FF FF FF FF
FF FF FF FA DE C5 AC 94
7B 62 4A 31 1C 0A 00 00
SPE 0
SPE 1
SPE 2
SPE 3

MultiMulti--resolution Subdivisionresolution Subdivision
Detail vector
Base Mesh
Decompose
Into 1-rings
PPE
SPE1
Kernel()
SPE0
Kernel()
SPE7
Kernel()…..
Data-parallel
System Memory
N 1-rings
…
…
Rn
.
R2
R1
R0
.
D6
D5
D4
D3
D2
D1
D0
Tj
.
.
T6
T5
T4
T3
T2
T1
T0
Store as
Ring stream
Triangles to GPU
GPU
Pixel
Processing
Frame Buffer
Vertex
Processing
Local or network connection
Dm

DemonstrationsDemonstrations
Raytracing
Terrain Rendering (TRE)
Cloth Simulation

Demo Platform: Cell Blade PrototypeDemo Platform: Cell Blade Prototype
Chassis
Blade
Deskside
Unit
Blade Server
– Dual Cell Processors (SMP), Support Logic,
Memory, Storage
– PCI Express 4X option port
– BladeCenter Interface ( Based on IBM JS20)
– Infiniband 4x (10Gbps) interconnect
Chassis
– Standard IBM BladeCenter form factor with:
– 7 Blades (1 blade/2 slots)
– 2 internal switches (1Gb Ethernet) with 4 external ports each
– Separate, external Infiniband Switch with optional FC port
Software
– Linux OS
– Tool chain and compilation support
– Additional IBM Software Development Tools and Cluster
Management software
– Client Systems
– IBM T41 Thinkpad (1.7 Ghz Pentium-M)
– Apple Mac-dual G5@2Ghz
Blade
BladeCenter Interface
PCI-Exp
Cell
Processor
South
Bridge
Memory
Cell
Processor
South
Bridge
Memory
IB
4X
IB
4X
HDD (HDD)
GbE GbE
Rack

Camera Shader
Example: Raytracing ArchitectureExample: Raytracing Architecture
OpenRT
Generate Tiles
Spatial Subdivision
K-d tree Traversal
Material Shading
Intersection Testing
Generate
Rays
View transorms
Recursive/Adaptive
Sorting
Spatial Subdivision
Structure
K-d Tree
Per object
& top-level
System Memory
•framebuffer
System Memory
•Texture Maps
•Run-time shaders
Tile pixels
Triangle-Ray pairs
Rays
SecondaryRays
PU Code
Potential execution on SPE
SPU code
Object Data
SPE iPPE
If intersect
false
true

Cell Optimized Ray Caster: Terrain Rendering EngineCell Optimized Ray Caster: Terrain Rendering Engine
30+ frames per second with only one Cell processor30+ frames per second with only one Cell processor
–– No graphics adapter assistNo graphics adapter assist
–– 1280x720 (HD 720P) resolution1280x720 (HD 720P) resolution
HD 1080P at 30+ frames per second via 2 way SMP CellHD 1080P at 30+ frames per second via 2 way SMP Cell
Advanced SPE shader functionAdvanced SPE shader function
–– Ray/Terrain intersection computationRay/Terrain intersection computation
–– Texture FilteringTexture Filtering
–– Normal computationNormal computation
–– Bump map computationBump map computation
–– Diffuse + Ambient lighting modelDiffuse + Ambient lighting model
–– Perlin Noise based cloudsPerlin Noise based clouds
–– Atmosphere computation (haze, sun, halo)Atmosphere computation (haze, sun, halo)
–– Dynamic multiDynamic multi--sampling (4sampling (4 –– 16 samples per pixel)16 samples per pixel)
–– Image based input (16 bit height + 16 bit texture)Image based input (16 bit height + 16 bit texture)
–– 29 KB of SPE object code29 KB of SPE object code
–– 224 KB of SPE local store data224 KB of SPE local store data
MM--JPEG compression via SPEJPEG compression via SPE
Performance scales linearly with number of available SPEsPerformance scales linearly with number of available SPEs
Written completely in C with intrinsicsWritten completely in C with intrinsics
Currently up and running on bring up systems!Currently up and running on bring up systems!

Vertical Ray CoherenceVertical Ray Coherence

Algorithm Mapped to Cell

Physically Based Modeling: Alias research prototypePhysically Based Modeling: Alias research prototype
Cell implementation of Alias cloth solver
– Compute the displacement of 3-D cloth mesh vertices in
response to various gravitational, collision and constaints
– Each simulation can occur on a separate SPE
Render results on commodity graphics adapter – locally
or over network
Courtesy of Alias Systems™
SPEN
.
.
.
input
output
SPE3
input
output
SPE2
input
output
SPE1
input
output
SPE0
input
output
System
Memory
PPE
Main
SocketMgr
Create SPE Treads
DMAIN
DMAOUT
VertexDisplacementsout
Position, orientation input
Triangle output
Forcevectorsin

Cell beyond the PS3Cell beyond the PS3
IBM support for custom systems and applications based on Cell
− Through IBM Engineering and Technology Services
Planned release (next several months) of architecture, simulator, and compiler to
enable Cell software development and evaluation in a large community
− Linux OS, compilers, debugger, full system simulator
− Open source and IBM alphaworks
Prototype system implementations and evaluation of markets beyond console
− Cell Processor Based Blades (acceleration and other apps.)
− CE devices (HDTV, home media server)
− Standard products for embedded applications
− Prototype reference designs for smaller systems

SummarySummary
Cell ushers in a new era of leading edge processors optimized for digital
media and entertainment
New levels of performance and power efficiency beyond what is achieved by
PC processors
Step towards HPC / game processor convergence

AcknowledgementsAcknowledgements
Sony Computer Entertainment
Toshiba Corporation
IBM STI Design Center:
Peter Hofstee
Barry Minor
Mark Nutter
Gerhard Stenzel, IBM Boeblingen Development Labs
Philipp Slusallek, Saarland University
Alias Systems:
Joyce Janczyn
Francesco Iorio
Jos Stam

Thank youThank you

Cell Technology for Graphics and Visualization

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