1. Subrata Mandal
4006 Samuel Way Cell: 503-840-8438; Home: 503-336-
1838
El Dorado Hills, CA-95762 E-mail: smandal77@hotmail.com
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OBJECTIVE
Principal Engineer at Intel seeking leadership position in semiconductor industry. A result-oriented Chip
Design Professional with 20 years of design & post-silicon validation experience at Intel in various
technical and management positions. Expertise includes:
♦ Serial I/O Design (SERDES) ♦ Driving Corporate Innovation Program
♦ Parallel I/O Design (e.g. DDR) ♦ Post-si Characterization / Validation
♦ Mixed signal Design ♦ Technical Leadership
♦ Package Design ♦ Strategic Leadership & Planning
♦ System Level Power Delivery ♦ Project Management
SUMMARY
Expertise in Analog Circuit Design, High Speed I/O Design, Mixed signal Design. Successfully managed
I/O design & circuit design on several Intel Microprocessor and Chipset projects. Well familiar with the
collateral requirements from stakeholder teams such as design automations, quality and reliability,
product engineering, DFT, analog validation & layout engineering. Hold 10 US patents (1 pending).
Received several awards at Intel including Intel Innovation award for contribution to microprocessor
projects. Managed teams across several Intel sites (including US, India, Germany & Mexico). Also
owned responsibility on package design. Worked on low power circuit design /transistor definition. Even
though managed fairly large size teams for last several years, still provide significant technical
contribution. Worked on Expat assignments in India & Mexico - assignments focused on developing
design & post-silicon validation teams in international geos.
PROFESSIONAL EXPERIENCE
Server CPU I/O DFX Design / Analog Validation Manager Sept, 2010 – Current (Intel)
Introduced the idea of validation/ test friendly design at Intel. Designs need to be validation / test
friendly also in order to meet faster ‘Time To Market’. Responsible for defining and designing I/O DFX
circuits for various memory & serial I/O interfaces. Post-si Electrical Validation manager on High
Performance Computing CPU project. Used design expertise to influence the functional circuit
architecture / design decisions for facilitating faster readiness of IO and analog designs. The project
featured a Multi-chip module memory design – owned the post-si validation aspect also.
Server CPU Special Circuit Design Manager April, 2006 – August, 2009(Intel)
Lead the special circuit design effort in one of Intel’s latest high performance computing microprocessor
projects. The team was responsible for designing the high speed I/O circuits of different kinds (serial
I/Os as well as memory interfaces such as DDR). The team was also responsible for the design of
various kinds of analog circuits such clocking, DLL and thermal sensors. Responsible for general as
well as technical operations of a highly specialized team located across US sites & Germany.
Xeon Processor Design – Circuit Design Manager July, 2003 – March, 2006 (Intel)
Managed the I/O design cluster for Intel’s Xeon family processor (32 bit). As the I/O design manager,
managed a team of ~ 40 design engineers & layout engineers across multiple sites. The team was
responsible for the design of various CPU I/O interfaces, clock distribution. Technically fully involved in
the development of a high speed serial interface using clock data recovery – guided the team in
developing the spec and coming up with a robust design. The design used novel concepts on current
compensation, impedance compensation techniques. Also co-owned the power delivery analysis,

2. package design which are very critical design collaterals.
Owned the pre-silicon mixed signal validation of special circuits. Defined the DFX features and post
silicon validation plans. Defined the quarterly project execution plan, resource requirement, and team
training plan. Provided technical guidance on various design issues. Some of the critical challenges that
we had to resolve were: clock jitter reduction, low power design, power management etc. Implemented
current mode differential signaling techniques.
Pentium IV Chipset Project – Circuit Design Manager July, 2001 – June, 2003 (Intel)
Managed the complete Circuit Design aspect of this project with a team of ~20 design Engineers and
15 layout engineer. I was responsible for the custom design of various I/O interfaces: AGP (Graphics
Port), Hub Link, DDR400 & Front Side Bus (system bus)800. Apart from the I/O interfaces my team also
owned the PLL & SRAM development. Interfaced with the signal Integrity, power delivery analysis &
package design teams – provided them with design collaterals and reviewed their work. Chaired the
analog validation forum on this project. Apart from the managerial responsibilities I was highly involved
in the technical aspect of the project.
Server Chipset Project – Circuit Design Manager August, 1999 – June, 2001 (Intel)
This was the first Intel chipset to feature DDR interface. This project was a cross site project that
required lots of communication skill and efficient planning. The Chipset included various I/O interfaces
like FSB400, DDR200, Hub Link – most of these I/O interfaces used source synchronous architecture
to increase the data band width. Managed a team of 12 engineers. I was also highly involved in the
technical aspect of the project. Particularly DDR interface needed technical innovation. This was the
only interface where strobe is not placed in the center of the data eye when the chipset is receiving the
data from the DIMMs. Developed an innovative technique which placed the strobe at the center of the
data eye. Also co-owned the power delivery, signal integrity, package analysis. Interfaced with the PV
& validation teams. My team was also responsible for PLL and SRAM design and clock distribution.
Server Microprocessor Project – I/O Designer Feb, 1998 – July, 1999 (Intel)
Owned the FSB output buffer design of this project. Since this was a server processor, the platform had
a multi-drop bus. Signal integrity posed significant challenges. Came out with innovative circuit solution
to resolve the signal integrity issue. Made sure that the design met system timings as well. (Details of
the work cannot be given here due to intellectual property security reasons)
Pentium III I/O Designer/ Failure Analysis Early 1995 – Jan, 1998 (Intel)
Took complete ownership of all the design work in Pentium III front side bus output buffer (133MHz).
The design used common clock architecture. Innovative circuit techniques were used to deliver
133MHz FSB. Also worked as a Failure Analysis & Fault Isolation engineer on Pentium Pro processor
project.
EDUCATION
University of Florida, Gainesville, Florida (Aug’ 91–Dec’ 94) Dual engineering major graduate.
M.S. Electrical Engineering with specialization in Microelectronics
M.S. Materials Science & Engineering. Specialization in Semiconductors and Electronic Materials (Also
completed some of the key requirements towards PhD in Electrical Engineering)
PATENTS/AWARDS
 10 US patents (1 pending) on High Speed I/O Circuit and Custom Circuit Design. Several of
these patents have been used on Intel Microprocessors and Chipsets.
 Received Intel Innovation award at Intel for innovative design on Xeon server Microprocessor.
 Received several other awards at Intel for contribution to Microprocessor and Chipset projects.
 US patent list - continued on next page….

3. US PATENT LIST OF SUBRATA MANDAL
Title Grant Date Grant Number
METHOD AND APPARATUS FOR CALIBRATION OF A DELAY
ELEMENT
27 Sep 2005 6,950,770
GATED RING OSCILLATOR-BASED DIGITAL EYE WIDTH MONITOR
FOR HIGH-SPEED I/O EYE WIDTH MEASUREMENT
18 Aug 2015 9,112,671
SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O
INTERCONNECT LINKS BY USING FINE TRAINING OF PHASE
INTERPOLATOR
06 Jan 2015 8,929,499
SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O
INTERCONNECT LINKS BY USING FINE TRAINING OF PHASE
INTERPOLATOR - PART 2
20 Oct 2015 9,166,773
DYNAMIC ADAPTION OF CONTINUOUS TIME LINEAR
EQUALIZATION CIRCUITS in PCIe AND OTHER HIGH SPEED I/O
CIRCUITS
28 Oct 2014 8,872,541
METHOD AND APPARATUS FOR DYNAMICALLY CONTROLLING THE
PERFORMANCE OF BUFFERS UNDER DIFFERENT PERFORMANCE
CONDITIONS
20 May 2003 6,566,903
METHOD AND APPARATUS FOR DYNAMICALLY CONTROLLING THE
PERFORMANCE OF BUFFERS UNDER DIFFERENT PERFORMANCE
CONDITIONS - PART 2
23 Sep 2003 6,624,655
METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE
OF BUFFERS USING A TRANSLATOR CIRCUIT
30 Jul 2002 6,426,651
SYSTEM AND METHOD FOR REDUCING OVER-SHOOT AND RING
BACK BY DELAYING INPUT AND ESTABLISHING A SYNCHRONIZED
PULSE OVER WHICH CLAMPING IS APPLIED
17 Feb 2004 6,694,444
CIRCUIT SOLUTION FOR VALID STROBE DETECTION DURING
MEMORY CONTROLLER READ TRANSACTIONS FROM THE DDR
MEMORY
21 Feb 2006 7,002,378
SOFT EV - A SHIFT LEFT BRIDGING POST-SI ELECTRICAL
VALIDATION AND PRE-SILICON MODELS
PENDING