Simulation of Vertical Transistor and Ge Gate FET

GIEE, National Taiwan University 1
垂直式柱狀電晶體及鍺環繞式閘極電晶體之模擬
研究
Simulation Study of Vertical Pillar Transistor and Ge Gate-
All- Around FET
Yu Chun Yin
Advisor: C.W Liu, Ph.D.
Graduate Institute of Electronics Engineering
National Taiwan University

Outline
• Pillar transistors for high density DRAMs
• A low leakage junctionless vertical pillar
transistor
• Simulation study of Ge gate-all-around FET
• Scaling analysis of double- gate MOSFETs
considering the effect of high-k dielectrics

Pillar transistors for high
density DRAMs

Cell Transistor: History and Future
Vertical pillar transistor is the most promising candidate for the high
density DRAMs

Gate-all-around
The ultimate scaled device
Advantages:
 Good scaling properties:
a. excellent electrostatics integrity including subthreshold swing and DIBL
b. better short channel control
the leakage can be well controlled
with suitable threshold voltage.
 3D vertical structure provides high density array architecture: 4F2 memory cell
Vertical Pillar Transistor
1Slope
SS

Samsung 2011

Electrical challenges of VPT in DRAM
 The floating body effect remains as an obstacle in realization of the
vertical cell transistor due to the hole accumulation in the body which
results in off leakage failure.
S. Hong, 2010 IEDM
FBE

Floating Body Effect of VPT in DRAM
BLH BLL
Charged
body as
BJT base
B
E
C
BJT
current
turns on
+ +
SNSN

Solution to Floating Body Effect in VPT
 To minimize the gate induced
drain leakage (GIDL) current by
underlapped top source/drain.
 To reduce the barrier height for
hole between the body and the BL
by using SiGe layer.
Underlapped
top S/D
SiGe Layer
bottom S/D
SN
BL
Simulated device structure

0.00 0.05 0.10
0.0
0.5
1.0
1.5
E(MV/cm)
Z
Overlapped Drain
Underlapped Drain
 The underlapped Drain is far from the Gate. Thus it will reduce the
electric field between the drain and the channel. Suppression
of Leakage current
Leakage of Different top S/D Design
0.0 0.3 0.6 0.9 1.2
1E-17
1E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Overlapped Drain
Underlapped Drain
Draincurrent(A) Gate Voltage
Ioff reduce 2
orders.
Vds=1v

Band Diagram along Channel Direction
 The barrier for hole is smaller in SiGe layer than Si,
delaying the hole accumulation.
A
A’
-0.035 0.000 0.035 0.070
-1.0
-0.5
0.0
0.5
Energy(eV)
Z (m)
Ec
Ev
Si0.8Ge0.2
Si
Ev offset≈0.15(eV)
A’A
SN
BL

Transient Simulation of VPT Cell
Cell Capacitor = 1V
(data ”1” )
Bit Line
BLH 1V BLL 0V
Gate
Operation Condition:
1. Cell Capacitor data “ 1” is
written (1 volt)
2. Bit Line switch between
BLH and BLL
3. WL is off (Vgs=0)
 SiGe source and underlapped drain design can help
suppress the FBE in dynamic operation.

A Low leakage Junctionless Vertical
Pillar transistor

Why junctionless MOSFET?
• Uniform doping concentration in the channel and the
Source/Drain
Simpler process flow:
 n-type implant + activation
 Gate dielectric + gate stack
 Gate patterning
 Contacts
 All other intermediate implant after gate patterning( halo , S/D)
 Thermal annealing for activating the implant above
N+
GateGate
PN+ N+
Inversion mode MOSFET Junctionless transistor
Get rid of the problem of junction formation!!!

Conduction mechanism
Inversion mode Junctionless
This new type of junctionless transistor shows almost identical
electrical characteristics as the regular inversion mode MOSFET.
N+
GateGate
PN+ N+

Flat band Fully depleted
The entire semiconductor region becomes neutral.
:gs thV V
:gs fbV V
:gs thV V The bulk current flows in the neutral region (region is not
depleted ).
The device is turned off as the fully depleted condition is
approached.

The doping concentration in Junctionless devices is usually > 1019cm-3 for sufficient
amount of on-current. However, the depletion condition must be satisfied as the devices
are turned off. Therefore, the thickness of device must be smaller than 20nm.
Fully depleted channel
Channel doping
1019 cm-3

Leakage in Junctionless Transistor
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
1E-16
1E-14
1E-12
1E-10
1E-8
1E-6
1E-4
Id(log(A))
Gate Voltage (Volt)
diameter=15nm
channel doping=10
19
cm
-3
1fA/Cell is
required for
DRAM
application
Low leakage design is needed!!!
our work: recessed drain designJunctionless
transistor w/o
r-drain design

Structure of Junctionless VPTs
R-drain
design

Comparison of JL and inversion-mode VPTs
With recessed drain design, the leakage is well suppressed.
With r-drain design

Effect of the diameter of the r-drain(d)
When d=6nm ,QM
effect will cause severe
degradation of on-state
current

Effect of the diameter of the r-drain(d)
-50 0 50 100 150
-2.0
-1.5
-1.0
-0.5
0.0
0.5
d=6nm
d=12nm
Energy(eV)
Channel direction(nm)
Tox_r-drain is 4nm
JLT with larger d will
suffer larger drain
control over channel, and
the tunneling width of
the device with d=6nm is
longer for 1nm than the
one of the device with
d=12nm ,i.e smaller
GIDL.
Channel
direction

Effect of the thickness of the replacement oxide
d=8 nm is chosen.
With larger Tox_r-drain
the GIDL is smaller.
The on-current will not
degrade drastically.
Tox_r-drain
E-field in Si body

E-field and BTBT generation rate
 The peak electric field in JL with r-drain design is mainly located in the oxide.
E-field B2B generation rate
r-drain
design

Transient Simulation
The GIDL of the
VPT with r-drain
design is significantly
suppressed to the
order below 10-16 A.
As a result, the
dynamic retention
characteristics is
improved by applying
the recessed drain
design.
WL=0 V(cell transistor is truned off)

Summary
 Inversion-mode VPT with underlapped drain design and SiGe
layer which reduces the hole barrier near BL can suppress the
GIDL and the floating body effect in dynamic operation.
 A low leakage junctionless VPT is demonstrated by reducing
the diameter (d) of the drain near the channel with recessed
oxide. The GIDL of the cell transistor is well suppressed.
Dynamic retention characteristics is also improved due to the
suppressing BJT parasitic current during the variation of bit
line bias.

Simulation study of Ge gate-all-
around FinFET

 Ge – easier integration on Si
 Ge has the highest hole mobility and is experimentally demonstrated on p-FET.
 Although the bulk Ge has higher electron mobility, the n-FET still has low mobility
in experiment.
Si Ge GaAs InAs
Electron
Mobility (cm2/V-
s)
1600 3900 9200 40000
Electron m*/m0
mt: 0.19
ml:0.916
mt: 0.082
ml:1.64
0.067 0.023
Hole Mobility
(cm2/V-s)
430 1900 400 500
Hole
m*/m0
mHH: 0.49
mLH:0.16
mHH: 0.28
mLH:0.044
mHH: 0.45
mLH:0.082
mHH: 0.45
mLH:0.35
Bandgap (eV) 1.12 0.66 1.42 0.36
Permittivity 11.8 16 12 14.8
High Mobility Ge Channel

Good Old MOSFET Nearing Limits
Vt , SS and Ioff are sensitive to Lg
higher design cost
higher Vt,Vdd, hence higher
power consumption
Finally painful enough for
change
0.00 0.25 0.50 0.75 1.00
1E-11
1E-9
1E-7
1E-5
1E-3
DrainCurrent
Gate Voltage
Size
shrink
Chenming Hu , Univ. of California

Gate
Drain
Sourc
e
Insulator
Cg
Why Vt Variation and SS are So Bad
MOSFET becomes “resistor ” at very small L – Drain
competes with Gate to control the channel barrier.
Cd
0.00 0.25 0.50 0.75 1.00
1E-11
1E-9
1E-7
1E-5
1E-3
DrainCurrent
Gate Voltage
Size
shrink

Reducing EOT is Not Enough
Leakage Path
Gate
DrainSourc
e
Gate cannot control the leakage current paths that are
far from the gate

Gate
Gate
DrainSource
Eliminate Semiconductor far from Gate
FinFET body is a thin fin.
Fin Width
Fin Height
Gate LengthA thin body controlled by gate from
more than one side.

Device Structure (TEM)
50 nm SOI
TiN
Ge
GeO2/Al2O3
Si Si
Ge S/D
and
channel
Gate Length
The device is fabricated utilizing anisotropic etching process on an
epitaxial Ge layer on SOI. Then the interface is removed and the triangular
channel is formed.

Structure of Simulated Device
P+ -type
Ge
Si
Triangular Ge Fin 52nm
104nm
Cross section of the
triangular Ge Fin which is
wrapped by gate.Gate Length=180nm
FinWidth=52nm
FinHeight=104nm

Channel
direction
How to turn off the device?
The accumulation-mode device can be turned off as the channel region
is depleted. And there will be a hole barrier that suppresses the flow of
the hole.
Accumulation mode device
@ off state

Transfer Curves of the triangular Ge FinFET
-2 -1 0 1 2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Vd = -1V
Vd = -0.5V
Vd = -0.5V (TCAD)
Weff
/Leff
(nm) = 260/180
Wfin
(nm) = 52
S.S.=140mV/dec
EOT=5.5nm
Vth=0.007V
Draincurrent(A/m)
Gate voltage (V)
Ion/Ioff~1x105
-1.5 -1.0 -0.5 0.0
VG-VT=0
VG-VT=-0.5
VG-VT=-1
VG-VT=-1.5
VG-VT=-2
0
0
50
100
150
200
250
300
TCAD
DrainCurrent(uA/um)
Drain Voltage
From Id-Vg :Ion/Ioff =105 and SS=130mV/dec are obtained.
And Ion=235μA/ μ m
From Id-Vd: Saturation regime is observed.
With the fitting curves by TCAD
EOT=5.5nm
Dit=2*1012 cm-2eV-1
The large of Dit=2*1012
cm-2eV-1 for EOT=5.5nm is
responsible for SS.

Short Channel Effect
40 60 80 100 120 140 160 180 200 220
0.4
0.3
0.2
0.1
0.0
ThresholdVoltageRolloff(V)
Gate Length (nm)
GeTriangular TCAD
GeRectangular TCAD
40 60 80 100 120 140 160 180 200 220
120
160
200
240
280
320
360
400
SS(mV/dec)
Gate Length(nm)
Ge Rectangular
Ge Triangular
Leff
/Wfin
=183/52
52nm
104nm
52nm
104nm
Triangular FinFET provides
better short channel effect
suppressing.

modeling by analytical solution
( , ) ( )th g ds th thV L V V longchannel V  
2
1 32
( ) sin( )cos( )
2
exp( )[ ( ) ]
2
gs
th c ds c c
c eff eff
eff
ms ms ds ms
d
V
V V x z
A T H
L
V
L
 

 
   

   

   
2 2
1
1 0.5
( ) ( )
d
eff eff
L
T H


Pei, G., et al. FinFET design considerations based on 3-D simulation and analytical
modeling. Ieee Transactions on Electron Devices
4
( )
2
( )
si
fin fin ox
ox
si
fin fin ox
ox
Teff T T T
Heff H H T




 
 
SCE
,
,or
exp( )
2
eff
d
L
L

finTfinH
effL
exp( )
2
eff
d
L
L

Then SCE can be
suppressed
thV
Tfin
Hfin

Modeling by analytical solution
20 40 60 80 100 120 140 160 180 200 220
0.4
0.3
0.2
0.1
0.0
ThresholdVoltageRolloff(V)
Gate Length (nm)
GeTriangular modeling
by effective rectangular
GeTriangular TCAD
GeRectangular modeling
GeRectangular TCAD
Hfin=104nm
52nm
52nm
104nm
Hfin=104nm
Average
FinWidth
27nm
vs Triangular FinFET provides better
SCE control because of its smaller
effective FinWidth(Tfin).

Scaling analysis of double- gate
MOSFETs considering effect of
high-k

Scaling with different high-k dielectrics
10 20 30 40 50 60
60
70
80
90
100
Subthresholdswing
Effective gate length
k=340
model
k=340
TCAD
k=10.60
model
k=10.60
TCAD
Structure: Si channel ,Double Gate
TSi=8nm,EOT=0.9nm,VDS=0.8V
k of insulator=34 (Red)
Tinsulator=8 nm (physical thickness)
k of insulator=10.6 (Black)
Tinsulator=2.5 nm (physical thickness)
0
0
The DG device with thicker insulator is more difficult to be scaled .
The value of k must be chosen carefully!

Analytical solution
tan( ) tan( )
2
insulator semiconductor insulator
semiconductor
t t  
  

 λ is an indicator of the short channel effect and can be depicted by
The shortest gate length must larger than 1.5 λ for DG devices.
exp( )
2
gateL


2 11
{1 2 [1 ( ) ] exp( )} 60 /
28 10
2 2
ds g
g ds
V L
SS B mV dec
E V kT
q q



    
 
insulatort
semiconductort
insulator
semiconductor
Liang, X.P. and Y. Taur, A 2-d analytical solution for SCEs in DG MOSFETs. Ieee Transactions on Electron Devices, 2004.
51(9): p. 1385-1391
, 2semiconductor insulatort t  

vs dielectric constant (insulator)
10
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
EOT=0.9 nm tsi
=12nm
EOT=0.5nm tsi=12nm
EOT=0.9nm tsi
=8nm
EOT=0.5nm tsi
=8nm
nm
Dielectric Constant(insulator)
20 30 40
Scaling length
 As EOT is chosen, Tsi
As Tsi is chosen, EOT
As the Tsi and EOT is
chosen the value of k
Physical oxide thickness
needs to be scaled too!





vs dielectric constant (insulator)
10
10.0
12.5
15.0
17.5
20.0
EOT=0.5nm tge
=12nm
EOT=0.5nm tsi=12nm
EOT=0.5nm tge
=8nm
EOT=0.5nm tsi
=8nm
nm
20 30 40
Scaling length
The Ge channel has
larger scale length than the
Si channel does with the
same EOT and finwidth
due to its larger dielectric
constant (16 ).

0

Summary
 A new kind of Ge gate-all-around FinFET is fabricated. The
triangular-channel FinFET will provides better SCE control
than regular rectangular-channel FinFET because of its
smaller effective FinWidth(Tfin).
 As the EOT, FinWidth are chosen, the double-gate device with
thicker insulator is more difficult to be scaled due to the
weaker normal electric field.Therefore, the value of k must be
chosen carefully. The high-k dielectric of k=10~20 can be
applied without severe SCE.

Back up

Body Effect
Ec
Ei
Ev
EF
фB
FD PD
Vt=VFB +2фB +qNAW/ Cox If there is body potential Vb,
Surface Bending
Wdm

FD vs PD
• 1. How can the disappearance of the kink in
the thinner(FD) devices be explained?
Vt in FD is not sensitive to Vbody.
2. Since the Vbody induced in FD devices is
still substantial , a significant BJT action sill
can occur.

0.00 0.25 0.50 0.75 1.00
0
100
200
300
400
500
600
700
800
900
1000
Ids(uA/um)
Vds
PD D=40NM
FD D=16NM
Vg-Vt=1v
Body: Doping 5e18 (p type)
S/D : 2e19 (n type)
Lg :140nm
Wdm=15nm
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
0
500
1000
1500
2000
2500
3000
Ids(uA/um)
Vds
PD D=40NM
FD D=16NM
Vg-Vt=1v
BJT mode

Breakdown Voltage Delaying with SiGe
BL
Si0.8Ge0.2
Si
• Hole accumulation in the body of device with SiGe layer is less
than the one without, delaying the BJT parasitic current
occurring.
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
2.0x10
-5
4.0x10
-5
6.0x10
-5
8.0x10
-5
1.0x10
-4
Draincurrenyt(A)
Drain Voltage (Volt)
Si Source
SiGe Source
BJT
operation
dominates
@ Vgs=1v
49

Strain Distribution of Insert Channel
0 20 40 60 80
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
strain(%)
z(nm)
tensile strain
ANSYS Simulation
• Benefits from enhancement of electron mobility
50

Si
Substrate
Fully strained SiGe source
Si
channel
Tensil
e
strain
Mechanism of strain distribution
The mismatch between
Fully strained SiGe
source and Si channel
result in tensile strain
in Si channel which
can enhance the
mobility in nMOSFET.
51

0.8 1.0
10
-16
10
-14
10
-12
10
-10
10
-8
10
-6
QM: open sybol
CLASSICAL: Line
Id(A)
R-Drain Tox_r-drain=4nm
Vds=1 V
Id(log(A))
Gate Voltage (Volt)
JL w/o R-Drain
JL with R-Drain d=12nm
2.0x10
-6
4.0x10
-6
QM

10
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
EOT=0.9 nm tsi
=12nm
EOT=0.5nm tsi=12nm
EOT=0.9nm tsi
=8nm
EOT=0.5nm tsi
=8nm
nm
20 30 40
2
tan( )tan( )
2
2 11.7*
3.9
2 11.7
3.9
insulator semiconductor insulator
semiconductor
insulator
insulator
insulator insulator
t t
eot tsi
d tsi
eot
d
  
  




 

 
 
As tsi is chosen, with the larger eot , the slope will be larger
As eot is chosen ,with the smaller Tsi ,the slope will be larger
, 2semiconductor insulatort t  

10 20 30 40 50 60 70 80 90 100 110
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
ratioofLgtoFinwidth
Gate length
EOT=0.9nm =10 (Si channel)
Intel FinFET(tri-gate) Lg=30nm (Si channel)
EOT=0.5nm =19.5(Ge channel)
EOT=0.5nm =19.5(Si channel)

Simulation of Vertical Transistor and Ge Gate FET

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