3. MSI Counter
• 74LS163 characteristics
– edge-triggered
– synchronously presettable
– cascadable
– count modulo 16 (binary) 74x163
• Synchronous Reset
(Clear) input that overrides
all other control inputs
– active only during the rising
clock edge
3
10. Counter Operation
• Free-running ÷16
• Count if ENP and
ENT both asserted
• Load if LD is asserted
(overrides counting)
• Clear if CLR is asserted
(overrides loading and
counting)
• All operations take place on
rising CLK edge
makes it free-running
• RCO is asserted if ENT is
asserted and
Count = 15
10
11. Free-Running 4-Bit ’163 Counter
• “divide-by-16” counter
• RCO is asserted if ENT is asserted and Count = 15
11
15. Cascading Counters
• For modulus greater than 16
• RCO (ripple carry out) is asserted in state 15, if ENT is asserted
15
16. Decoding Binary-Counter States
• A binary counter may be combined with a decoder to obtain a set of
1-out-of-m coded signals, where one signal is asserted in each
counter state
Useful when counter outputs are used to control a set of devices
A different device is enabled in each counter state
In this approach each output of the decoder enables a different device
The next slide shows the 74163 wired as a modulo 8 counter
combined with a 74138 (3 to 8 decoder)
The decoder output provides eight signals, each one representing a
counter state
16
18. Decoding Binary-Counter States
• The next slide shows a typical timing diagram for this
circuit
• Each decoder output is asserted during a corresponding
clock period
• The decoder outputs may contain “glitches” on state
transitions where two or more counter bits change
• This happens even though the 74163 outputs are glitch free
and the 74138 does not have any static hazards
• In a synchronous counter like the 74163 the outputs don’t
change exactly at the same time
• Moreover multiple signal paths in a decoder like 74138
have different delays; thus the output may have glitches
• This problem is an example of functional hazard
18
20. Glitch-Free Outputs
• In most applications these would be used as control inputs to
counters, registers and other edge triggered devices
• In such a case there is no problem as the glitches occur after
the clock tick
• They would be a problem if applied to latches
• They would also be a problem if utilized as a clock
• One way to “clean-up” these glitches is to connect the 74138
decoder output to another register
• This register would sample the stable decoded outputs on the
next clock tick as shown in the next slide
• In this case the final outputs would have to be renamed to
account for the one clock tick delay through the register
20
22. 74161 MSI Counter
• The 74163 is fully synchronous
• Some applications require an asynchronous
clear function
• That is provided by 74161
• It has the same pinout as 74163
• Its CLR_L input is connected to the
asynchronous clear inputs of its flip flops
23. Modulo-10 Counters
• From the 74LS163 “family” – the 74LS160
– 74LS160 in free-running mode
– Duty cycle of QC and QD is not 50%
23
24. Modulo-10 Counters
• 74LS160 state diagram
• The 74LS160 (and
74LS162) can be preset
to any state, but will not
count beyond 9.
• If preset to state 10, 11,
12, 13, 14, or 15, it will
return to its normal
sequence within two clock
pulses.
• 74160 has asynchronous
clear as in 74161
24
25. Up/Down Counters
• A 3-bit binary up/down counter (block diagram)
QA
Clock QB
Counter Count
QC
UP / DOWN
25
28. Up/Down Counters
• This circuit is a 3-bit UP/DOWN synchronous counter using
JK flip-flops configured to operate as toggle or T-type flip-
flops giving a count of zero (000) to seven (111) and back to
zero again.
• An additional input determines the direction of the count,
either UP or DOWN and the timing diagram gives an
example of the counters operation as this UP/DOWN input
changes state.
28
30. Up/Down Counters
• The 74LS169 is a fully
synchronous 4-stage
up/down counter
• Includes:
– a preset capability for
programmable
operation
– carry lookahead for
easy cascading
– a U/ D input to control
the direction of
counting
30
33. Up/Down Counters
• 74LS169 logic symbol
• Functions similar to 74163
• Difference is that its carry output
and enable inputs are active low
• It is an up/down counter
• It counts ascending or descending
binary order depending on the value
of input signal UP/DN
• Counts up when UP/DN is 1
• Counts down when UP/DN is 0
33
