2. Design of a Beta-Multiplier Voltage Reference for
Glucose Sensor
Mohd Ishtiaque Ibn Hossain
Department of Electrical Engineering and Computer Science
University of Tennessee, Knoxville TN, USA
18th April , 2016
Master of Science Project Defense

3. 3
Outline
 Introduction and Motivation
 Design of a Beta-Multiplier Voltage Reference
 Changes in Reference Voltage (VREF) with Supply (VDD)
 Changes in Reference Voltage (VREF) with Temperature
 Changes in Reference Voltage (VREF) with Process Variation
 Comparison of Beta-Multiplier Voltage Reference with Bandgap Reference
 Beta-Multiplier Reference in a Voltage Regulator
 Results and Discussions

4. 4
Glucose Monitor
 According to World Health Organization, the number of people with diabetes
was 422 million in 2014[1]
 WHO projects that diabetes will be the 7th leading cause of death in 2030
 Preventive treatment costs per person approximately $12000 annually
[1] http://www.who.int/mediacentre/factsheets/fs312/en/
[2] http://www.medtronicdiabetes.com/products/continuous-glucose-monitoring
Glucose monitor[2]

5. 5
Block Diagram of Glucose Sensor System
Block diagram of the glucose sensor system.

6. 6
Voltage Reference
 A general-use (ideal) voltage reference is a circuit used to generate a fixed
voltage VREF , that is independent of power supply voltage VDD (where VREF < VDD) ,
temperature and process variation.
 Application:
Voltage references are used in regulators, which is an integral part of almost all
analog and digital devices.
 Voltage Reference Design Topologies:
• Voltage reference using MOSFETs and resistors
For e.g. Beta Multiplier Reference
• Voltage reference using parasitic diodes
Also known as Band-Gap Reference
 Voltage References Design Challenges:
Generate fixed voltage (VREF), that is independent of the
• Power supply
• Temperature
• Process variation
In short, an ideal voltage reference is independent of PVT

7. 7
Design of Voltage Reference using Beta Multiplier
R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 3 edition. Piscataway, NJ : Hoboken, NJ: IEEE Press, 2010.
Voltage Reference using Beta-Multiplier Topology
VGS1 = VGS2 + IREF.R
β2 = K. β1
IREF
Vreg
Vbiasn
VDD

8. 8
Voltage Reference using Beta Multiplier (Schematic)
Voltage Reference using Beta-Multiplier
MSU1
MSU2
MSU3
M1 M2
M3 M4
MA1 MA2
MA3 MA4
R

9. 9
Simulation Result of Voltage Reference as a function of Supply
Result: Constant VREF for varying power supply
VDD (V)
VREF(mV)

10. 10
Simulation Result of Voltage Reference as a function of Temperature
Result: Constant VREF for varying Temperature
VREF(mV)
Temperature (C)

11. 11
Monte Carlo Simulation of Voltage Reference as a Function of Process
Result: Average = 661.2mV, Standard Deviation = 26.9mV
VDD (V)
VREF(mV)
VREF (mV)
No.ofpoints

12. 12
Voltage Reference using Beta Multiplier (Layout)
Layout area: 33.6 X 47.31 µm2

13. 13
Monte Carlo Simulation of Voltage Reference as a Function of Mismatch
Result: Average = 660.9mV, Standard Deviation = 8.9mV
VDD (V)
VREF(mV)
VREF (mV)
No.ofpoints

14. 14
Band-Gap Reference Circuit
Schematic of a Bandgap Reference circuit.

15. 15
Simulation Result of Voltage Reference as a Function of Supply
Result: Constant VREF for varying power supply
VDD (V)
VREF(mV)

16. 16
Simulation Result of Voltage Reference as a Function of Temperature
Result: Constant VREF for varying temperature
Temperature (C)
VREF(mV)

17. 17
Monte Carlo Simulation of Bandgap Reference as a Function of Process
Result: unstable VREF due to process variation
VDD (V)
VREF(mV)

18. 18
Voltage Regulators
 Voltage Regulators
A voltage regulator generates a fixed output voltage
of a preset magnitude that remains constant regardless
of changes to its input voltage or load conditions
 Voltage Regulator topology
A voltage reference is used with an op amp to
generate a regulated voltage.
VREG
Schematic of a Voltage regulator circuit.
In ideal condition (op-amp has
infinite open loop gain),
VREG = VREF . ( 1 + RA /RB )

19. Analog VLSI and Devices Laboratory 19
Voltage Regulators

20. 20
Schematic of Voltage Regulator
Schematic of a Voltage regulator circuit.
Beta-Multiplier Voltage Reference Op-Amp

21. 21
Regulator Output (VREG) Analysis
Result: for 400mV change is Supply voltage, VREG changes by 15mV
VREF
VREG
VDD (V)
VREG(V)VREF(mV)
VREG
VREF

22. Regulator Output (VREG) Analysis
Result: for 20°C Change in temperature, VREG changes by 8mV
VREF
VREG
Temperature (C)
VREF(mV)VREG(V)
VREG
VREF

23. PVT corner Analysis
Result: VREF varies ±9%
VDD (V)
VREF(mV)

24. Target simulated
Supply (V) 1.8 1.8
VREF (mV) 660 660.7
IREF (µA) 6.6
Power Consumption (µW) 11.8
ΔIREF (µA) with VDD=10% around nominal value no change
ΔVREF (mV) with VDD=10% around nominal value no change
ΔIREF (µA) with R=10% around nominal value 0.07
ΔVREF (mV) with R=10% around nominal value 6
TCVREF (ppm/°C) 1000
TCIREF (ppm/°C) 2000
Standard Deviation in Monte Carlo Simulation (1000 points) of VREF as a Function of Process (mV) 27
Standard Deviation in Monte Carlo Simulation (1000 points) of VREF as a Function of Mismatch (mV) 9
Regulator Output VREG (V) 1.1 1.11
Regulator Output VREG (V) @37°C 1.1 1.114
ΔVREF (%) in PVT Corner Simulation ±9%
Summary

25. Questions
Mohd Ishtiaque Hossain
mhossai7@vols.utk.edu
Thank You