This paper presents a binary topology of Multimodule level inverters produce a staircase output voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many number of semiconductor switches is main drawback of multilevel inverters. The MLI can be classified as two method, one is symmetric and another asymmetric converters. In symmetrical multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm. In this paper, a discrete binary topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete binary topology. The working operation and performance of the proposed multilevel inverters studies has been verified by simulation of using SIMULINK / MA TLAB results.

1. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
Hybrid Topology of Asymmetric Cascaded
Multilevel Inverter with Renewable Energy Sources
ABSTRACT:
This paper presents a binary topology of Multimodule level inverters produce a staircase output
voltage from renewable DC voltage sources. The MLI (Multi Level Inverter) Requires many
number of semiconductor switches is main drawback of multilevel inverters. The MLI can be
classified as two method, one is symmetric and another asymmetric converters. In symmetrical
multilevel inverter can apply same voltage level to all cascaded circuit, in asymmetric multilevel
inverters can be vary input source voltage at each cascaded H-bridge by using binary algorithm.
In this paper, a discrete binary topology for multilevel converters is proposed using cascaded
sub-multilevel Cells. This sub-multilevel converter can produce sixty three levels of voltage
from five discrete DC source. The Total Harmonic Distortions (THD) is minimized by discrete
binary topology. The working operation and performance of the proposed multilevel inverters
studies has been verified by simulation of using SIMULINK / MA TLAB results.
KEYWORDS:
1. Asymmetric Cascaded Multilevel Inverter
2. Reduction Of Thyristor Switches
3. Minimized Total Harmonic Distortions
4. High Output Gain
5. Discrete Binary Topology
SOFTWARE: MATLAB/SIMULINK

2. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
BLOCK DIAGRAM:
Fig 1 General Block Diagram Of Cascaded MLI

3. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
EXPECTED SIMULATION RESULTS:
Fig 2 Harmonic Reduction Of Cascaded Multilevel Inverter
Fig 3 Thyristor Pair ON State Position of Positive and Negative Sine

4. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
Switching Techniques
Fig 4 Switching Techniques, Output Voltage And Gate Triggering System
(G I ,G 2,G3,G4,G5) Wave Form of Cascaded Multilevel Inverter.

5. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
Fig 5 Output Voltage and Current Wave Form of Proposed Multilevel
Inverter
CONCLUSION:
In this paper, a discreet binary topology was presented for cascaded multilevel Inverter, which
has reduced number of thyristor switches. The suggested discreet binary topology requires
limited switches for synthesized output voltages. The hybrid topology of common h-bridge
cascaded multilevel inverter is proposed for variable AC output voltages and frequencies as per
given source input by using reduced no of switches to half than conventional inverter. Therefore,
the cost of proposed system reduced. As a result, the output voltage waveform presents very low
total harmonic distortion profile and provides better efficient. The application of this project is
ups and variable speed drives which result in high dynamic response for speed.

6. ELECTRICAL PROJECTS USING MATLAB/SIMULINK
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
For Simulation Results of the project Contact Us
Gmail: asokatechnologies@gmail.com, Website: http://www.asokatechnologies.in
0-9347143789/9949240245
REFERENCES:
[I] Jaison Mathew, K. Mathew, Najath Abdul Azeez, P. P. Rajeevan, and K. Gopakumar, "A
Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage
1M Drives," IEEE Transactions On Power Electronics, Vol. 28, No.8, August 2013.
[ 2] Dong Cao, Shuai Jiang, and Fang Zheng Peng, "Optimal Design of a Multilevel Modular
Capacitor-Clamped DC-DC Converter," IEEE Transactions On Power Electronics, Vol. 28,
No.8, August 2013.
[3] P.Roshankumar,P.P.Rajeevan,K.Mathew,K. Gopakumar, Jose I. Leon, and Leopoldo G.
Franquelo, "A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying
Capacitor Inverter and an H-Bridge," IEEE Transactions On Power Electronics, Vol. 27, No.8,
August 2012.
[4] Qin Lei, Fang Zheng Peng, and Shuitao Yang, "Multiloop Control Method for High-
Performance Microgrid Inverter Through Load Voltage and Current Decoupling With Only
Output Voltage Feedback," IEEE Transactions On Power Electronics, Vol. 26, No.3, March 20
II.
[5]M. R. Banaei and E. Salary, "Verification of New Family for Cascade Multilevel Inverters
with Reduction of Components," Journal of Electrical Engineering & Technology Vol. 6, No. 2,
pp. 245-254, 2011 D01 :IO.5370/JEET.2011.6.2.245.