Chip Design Trends

1. Chip Design Trend & Fabrication Prospects in India BY: Bibhuti Bikramaditya Technical Leader DCA Electronic System Design Pune

6. IC Design Technique from layout level to system level The introduction of HDLs have made possible the design of complete System on Chip(SOC), with the complexities rising from 1 million to 10 million transistors.Recently System C has been introduced for 100 million to 1000 millions of transistors.

7. IC Design Growth at frequency level The clock frequency increased for high performance micro processor and industrial micro controllers with the technology scale down. here motorola micro controler has been taken as the example used for high performance automotive industry applications.

8. Intel Microprocessor Growth Describes the evolution of complexity of intel@ micro processors in terms of no. of devices on the chip the pentium 4 processor produced in 2003 is 50 million MOS devices integrated on a single piece of silicon no larger than 2 x 2 c.m.

9. Evolution of Memory Size First 1 kb memory produced by Intel in 1971 , semiconductor memory have advanced both in density as well as performances. With the production of 256 Mb memories in 2000 and 1Gb in 2004 according to the estimates , it will expected to increase up to 16 Gb in 2008.

10. Evolution of Lithography Trend towards the smaller dimension has been accelerated since 1996. in 2007, the lithography is expected to decrease down to 0.07 um .

11. Evolution of silicon area for NAND Gate Fig shows how fabrication for Simple NAND gate become complex as its feature size is decreasing almost exponentially .

12. Typical Structure ICs

13. Moor’s Law Vs. IC Technology Growth First Law: Silicon Technology will double the number of transistors per chip every 18 months !!! all above example shows its validity. In other way ,its minimum feature size must decrease by a factor of 0.7 every three years

16. PLD Trend

17. Xilinx FPGA Architecture

18. CPLD Vs. FPGA Architecture PLA like Gate array like Density Low to medium Medium to high Speed Fast, predictable Application dependent Interconnect Crossbar Routing Power consumption High Medium

19. ASIC Vs. FPGA

21. New FPGA Revolution

22. New FPGA Revolution: SPARTAN 3 Recently Introduced

23. New FPGA Price Revolution Price of 100k gates over time

24. Cost Management through System Integration

27. DSP VLSI & Communication Trend is now to implement all DSP Function and algorithm into VLSI so as it could make complete chip being largely used for High speed Multimedia application, tele-mobile communication and GPS System DSP Performance and Flexibility: FPGA Solution

28. Conventional DSP Software VS. FPGA Performance advantage

29. Image Processing

30. Image Processing : MPEG-4 The Brilliant Engineers of DCA Electronic System Design is also working on complete Implementation Of MPEG-4 using VLSI and Embedded Technology

32. Auto motive Electronics Market Overview

33. Auto motive Applications

34. FPGA Solution for Car Manufacturers

35. CAR CUBE : Telematics Platforms from Acuna & Xilinx

36. CAR CUBE : Architectural Description

37. Auto motive Sector : Issues and Challenges

38. Auto motive Sector : In Vehicle Networking LAN: Local Area Network, CAN: Control Area Network

39. Auto motive Sector : MOST Application

40. Auto motive networks

41. Car Multimedia System

42. Security System: Encryption & Decryption AES Algorithm Implementation

43. Security System: Encryption & Decryption AES Algorithm Implementation

44. System On Chip Design : with Virtual Component System On Chip may contain both a system bus connect and Peripheral bus connect custom I/O block that provide functions not commercially available,may also be included In the recycling age, designing for reuse sounds like a great idea but with increasing requirements and chip sizes,its no easy task.

46. Bio Chips : A medical Revolution developed to sequence unknown genes and to study gene expression. but the working principle suggest that they can be used for engineering application that require parallel processing. DNA chips are proposed here as the physical substrate to store and evaluate a set of rules for knowledge based systems. In DNA chips, each cell uses millions of copies of DNA sequence called probes. The colors indicate that probes are different between cells

47. Bio Chips : Design Steps Fig(1) Single stranded DNA sequences Fig2 Nucleotide with pyrimidine base and Purine base Simplified Diagram for Fig3

48. Bio Chips : Design Steps Fig4:DNA sequence tagged with the quantum dots. Here half circle represent Single stranded DNA Sequence and Small dot is the quantum dot Fig5:Complementary probes and target bind to fluorescent DNA helix. In practice , there are millions of probes per cells ,so millions of targets are required to produce Fluorescent cell after hybridization Fig6: plant states are sampled and A/DNA Converter produce millions of two tagged DNA sequences. Small dot is quantum dot used to identify helix Fig7:DNA chip is injected with millions of tagged DNA strands. After Scanning the chip and processing the rules o/p is produced Fig8: DNA chip can be used to detect faults in the plant. State variables are sampled ,converted into DNA target and injected into chip. The green cells are fluorescent probes after being excited with UV light

50. Time Delay Neural Network : Phoneme Recognition (Speech Recognition) Fig1: component of Speech Recognition System Fig2:Neuron Unit Schematic Diagram Fig3: Error Signal Generator Schematic Diagram Fig4:Synapse Unit Schematic Diagram Used for storage and updates of weight Conclusion: Using Small dimension CMOS processes, such as 0.35 um ,a 5 mm by 5 mm chip could include up to 150 neurons, 150 synapses and 150 error signal generator unit to construct full time delay neural network for phoneme recognition, using just a Single Chip . This chip could then be interfaced with computer to generate fully generated phoneme recognition system

51. Neuro Chip : Design Dreams Recently revolutionary Invention of Neuro Chip wondered the world : if it mixed with our nervous system ,it will control Brain’s nervous system and then according to the program one can control on his thinking ability also. Are you not thinking that designing dream is also not impossible ? See my article in “The Times Of India” Education Times dated sept,30,03 on “VLSI DSP & Embedded Systems : Emerging Careers”

53. Chip Design Productivity Fig1: Actual No. of Transistors in millions per IC design. This data illustrates that there is little correlation between transistors count and engineering effort Fig2: Normalized Transistors count Vs. Persons week Fig 3: Factors Influencing IC Design Effort Design Productivity = output produced /labour expended = output per unit worker hour Manufacturing productivity = value added/labour expended = value added per unit worker hour. = (end product selling price- material cost of the product) worker hour = dollars per worker hour Chip design productivity ≠ transistor /gate per unit engineering effort. Chip design productivity = chip design complexity/ engineering effort. = complexity per unit engineering hour. = normalized transistors per person-hour.

54. Chip Design Fore cast 1.According to a Gartner forecast: 3 per cent growth in global semiconductor revenue ,2003 "after its worst fall ever in 2001." (2) India's chip design industry :revenues of Rs 1,500 crore ($ 300 million), (3) Indian Market Share : not up to the mark but in three-four years ,it will reach on standard mark. According to a Monster India.com report, "The integrated circuit (chip) design industry is pegged to grow into a multi-million dollar industry in India, thanks to the US slowdown." (4) Indian Design Industry: performing well and going global. large semiconductor vendors are growing their operations in India.

55. World Fabrication Industry Vs. Indian Fabrication Industry 5. Fab Industry: (a) Around 50 Fab lab Exist in the world,another 50 in near future (b) First fab lab by Intel Just open in Taiwan ,first in South Asia. (c) No Complete VLSI Fab Industry In India, (d) SCL ,Chandigarh has its own LSI Fab lab. (e) Proposal : Rs.1500 crore (for Indian Govt) (f) Recently Two Companies joined forces in Fab Industry like IBM/siemens for 64 Mb Technology and IBM, Siemens &Toshiba for 256 Mb Technology. 6.Huge Investment Required for Design and Fab Lab: According to Mr Girish of Texas Instruments, "It's not feasible for many small Indian companies to make sustained investments for a long period of time, which is required for product development (including the area of chips design/manufacture). I don't think we can do that now. Also, to get into full-scale manufacturing, the government should also take some efforts. It has to take a decision to shift manufacturing units to smaller towns instead of concentrating on the metros."

58. Conclusion: Despite all these stiff challenges , Chip Design Industry is growing not wittingly fast and are affecting even common mass to go nuclear as well as global . Indian Fabrication Industry is the biggest challenge and dream also . Let us see when this dream comes true.

59. The End