This document provides an overview and summary of the key concepts covered in the Nand2Tetris hardware course, including: 1. Digital logic concepts such as truth tables, logic expressions, gates, and Hardware Description Language. 2. Boolean logic gates like NOT, AND, OR, and XOR and how to build more complex logic functions from these basic gates. 3. Combinational logic circuits including binary addition, ALU, multiplexers, and demultiplexers. 4. Sequential logic circuits like registers, RAM, and program counters used to store state. 5. An introduction to machine language and computer architecture including von Neumann and Harvard architectures.

1. 計算機結構
( 習題： Nand2tetris 硬體部分 )
陳鍾誠
2017 年 9 月 2 日
本文衍生自維基百科

2. Chapter 0–Background
● Digital Logic
● Hardware Description Language

3. Digital Logic

4. Truth Table

5. Logic Expression

6. Gates

7. Composite Gates

8. HDL
(Hardware Description Language)
http://nand2tetris.org/chapters/appendix%20A.pdf

9. HDL

10. Hardware Simulator

11. NAND Gate

12. Karnaugh map (1)
https://zh.wikipedia.org/wiki/%E5%8D%A1%E8%AF%BA%E5%9B%BE

13. Karnaugh map (2)
https://en.wikipedia.org/wiki/Karnaugh_map

14. Karnaugh map (3)
https://zh.wikipedia.org/wiki/%E5%8D%A1%E8%AF%BA%E5%9B%BE

15. Exercise (1)
https://en.wikipedia.org/wiki/Seven-segment_display

16. Exercise (2)

17. Exercise (3)

18. Chapter 1 - Boolean Logic

19. Project 1: Elementary Logic Gates

20. Not

21. And

22. Or

23. Xor (1)

24. Xor (2)

25. Xor (3)

26. Mux (1)

27. Mux (2)

28. MUX (3)

29. MUX Chip
https://zh.wikipedia.org/wiki/7400%E7%B3%BB%E5%88%97IC%E5%88%97%E8%A1%A8

30. DMUX (1)

31. DMUX (2)

32. DMUX (3)

33. Not16

34. And16

35. Or16

36. Mux16

37. Or8Way

38. Mux4Way (1)

39. Mux4Way (2)

40. Mux4Way16
...

41. Mux8Way

42. Mux8Way16
...

43. DMux4Way (1)

44. DMux4Way (2)

45. DMux8Way

46. DMUX Chip

47. Chapter 2 - Boolean Arithmetic

48. Project 2: Combinational Chips

49. Binary Addition

50. 2's complement

51. Half Adder (1)

52. Half Adder (2)

53. Full Adder (1)

54. Full Adder (2)

55. Add16 (1)

56. Add16 (2)

57. Inc16
●Inc16 = Add16(in, 1)

58. ALU (1)

59. ALU (2)

60. ALU
● without handling of status outputs

61. ALU● complete

62. Chapter 3 - Sequential Logic

63. Project 3: Sequential Chips

64. DFF : D Flip-Flop

65. Bit ?

66. Bit

67. Register

68. RAM

69. RAM8

70. RAM64

71. RAM512 、 RAM4K 、 RAM16k ...
● Just the same way ...

72. PC (Program Counter)

73. PC (2)

74. PC (3)

75. Chapter 4 - Machine Language

76. Project 4: Machine Language Programming

77. Assembly (1)

78. Assembly (2)

79. Assembly (3)

80. Assembly (4)

81. Mult.asm

82. Assembly (I/O)
●Membory-Mapped I/O

83. Memory (mapped to device)

84. Fill.asm

85. Chapter 5 - Computer Architecture

86. Project 5: Computer Architecture

87. Von Neumann Architecture

88. Harvard architecture

89. Memory (1)

90. Memory (2)

91. Memory (3)

92. CPU (1)

93. CPU (2)

94. CPU (3)

95. CPU (4)

96. CPU (4)

97. Computer (1)

98. Computer (2)

99. Computer (3)

100. Computer (4)

101. It's your turn
●Do it yourself
●You can make it !