C&CPU

1. C & CPU
fea<feathertw@gmail.com>
2016.02.16

2. WHAT?
● A complete system
○ HW: CPU, BUS, Memory, Peripheral
○ SW: sssimple os
● Language
○ HW: verilog
○ SW: c & assembly

3. WHY?
● Background
○ know a little about C code
○ learning embedded system-stm32f4
● Motivation
○ know about how a computer system run
○ know about CPU and OS relationship

4. Target
● Define software need -> Implement necessary hardware
● Software
○ run basic c program
○ basic function of os kernel
● Hardware
○ CPU
○ BUS
○ Memory
○ Uart(only register)

5. Communicate
CPU
xUART
0
1
RX
TX
DATA FLAG ENABLE
iVerilog

6. Demo

7. Demo program
A program that can run a basic function of os, include
○ boot for c code environment
○ control kernel mode and user mode
○ set up user tasks
○ context switch
○ comunicate between tasks

8. Demo Enviroment
● Ubuntu 12.04LTE 32bit
● Icarus Verilog 0.9.5
○ sudo apt-get install iverilog
● nds32le-linux-glibc-V1 toolchain 2009 version
● git v1.7.9.5
○ sudo apt-get install git
● Python v2.7.3
● GTKWave v3.3.34
○ sudo apt-get install gtkwave

9. Setting & Run
● #Download toolchain from https://goo.gl/HPeM0H
● unzip nds32le-linux-glibc-V1-zip
● export PATH=$PATH:$(pwd)/nds32le-linux-glibc-V1/bin
●
● git clone https://github.com/feathertw/TiniSOC.git
● git clone https://github.com/feathertw/TiniOS.git
● git clone https://github.com/feathertw/TiniRUN.git
● cd TiniRUN/
● . run.sh

10. Hardware

11. CPU
I cache D cache I/O port
Master wapper
AMBA-AHB
IM DM Peripheral
Slave wapper Slave wapper Slave wapper
Architecture
Master wapper Master wapper

12. Refer:
1. AndesStar Instruction Set Architecture
2. Stm32(arm cortex-m)
3. MIPS 5 stages pipeline
Characteristics
1. 5 stages pipeline
2. write-through cache
3. jump cache & branch prediction
4. kernel mode & system mode
5. interrupt handle
6. systick timer
CPU

13. R-type
ADD, SUB, AND, OR, XOR,
SEB,SEH,SLT, SLTS, SRL, SLL,
SRA,SRLI, SLLI,SRAI, ROTRI
CMOVN,CMOVZ
I-type
ADDI, SUBRI,
ANDI, ORI, XORI,
SLTI, SLTSI
type3 MOVI, SETHI
Memory
LW, SW,
LWI, SWI,
LWI.BI, SWI.BI
BRANCH
BEQ, BNE,
BEQZ, BGEZ, BGTZ, BLEZ, BLTZ, BNEZ
JUMP J, JAL, JR, JRAL
MISC MTSR,MFSR,SYSCALL, IRET
“lmw,smw” change to ”lwi,swi” in compile time
Opcode

14. Jump cache
21 3 4 5
jump cache
0000 A1 $r0, $r1, $r2
0004 A2 $r0, $r1, $r2
0008 j Hello(0x10)
000c A3 $r0, $r1, $r2
Hello:
0010 A4 $r0, $r1, $r2
0014 A5 $r0, $r1, $r2
1 2 3 4 5
step1 j A2 A1
step2 A3 j A2 A1
step3 A4 A3 j A2 A1
1 2 3 4 5
step1 j A2 A1
step2 A4 j A2 A1
step3 A5 A4 j A2 A1
decodefetch
miss
hit

15. Jump cache test
_start:
j Reset_Handler
Reset_Handler:
la $r0, #1000
la $r15, #1
my_repeat:
beqz $r0, my_exit
addi $r0, $r0, #-1
j my_repeat
my_exit:
la $r15, #2
my_loop:
j my_loop
no jcache with jcache improve rate
4005cycles 3036cycles 24%
with jcache
no jcache

16. Branch prediction
S2
Predit Not
Taken
S0
Predit Taken
S1
Predit Taken
S3
Predit Not
Taken
Not taken
Not taken
Not taken
Taken
Taken
Taken
Not taken
Taken
0000 A1 $r0, $r1, $r2
0004 A2 $r0, $r1, $r2
0008 beq $r0, $r1 Hello(0x10)
000c A3 $r0, $r1, $r2
Hello:
0010 A4 $r0, $r1, $r2
0014 A5 $r0, $r1, $r2
1 2 3 4 5
step1 beq A2 A1
step2 A3 beq A2 A1
step3 A4 A3 beq A2 A1
1 2 3 4 5
step1 beq A2 A1
step2 A4 beq A2 A1
step3 A5 A4 beq A2 A1
miss
taken
hit-S1
taken
1 2 3 4 5
step1 beq A2 A1
step2 A4 beq A2 A1
step3 A3 A4 beq A2 A1
hit-S0
not taken

17. Branch prediction test
_start:
j Reset_Handler
Reset_Handler:
la $r0, #1000
la $r15, #1
my_repeat:
addi $r0, $r0, #-1
bnez $r0, my_repeat
nop
my_exit:
la $r15, #2
my_loop:
j my_loop
no bcache with bcache improve rate
3001cycles 2004cycles 33%
with branch prediction
no branch prediction

18. CPU
BUS-AHB
I cache
D cache
I/O port
IM
DM
Peripheral
2 cycle delay

19. Signal
for icache width
16-beat incrementing burst
2 cycle delay

20. Software

21. Toolchain
● nds32le-linux-glibc-V1
○ nds32le-linux-gcc
○ nds32le-linux-as
○ nds32le-linux-ld
○ nds32le-linux-objcopy
○ nds32le-linux-objdump

22. Memory
IM
DM
Peripheral
System
0x0000_0000
0x0100_0000
0x0200_0000
0x0300_0000
0x0E00_0000
0x0F00_0000
Memory map
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000,
LENGTH = 0x00040000
RAM (rwx) : ORIGIN = 0x01000000,
LENGTH = 0x00040000
}
SECTIONS
{
.text :
{
_stext = . ;
*(vectors)
*(.text)
_etext = . ;
} > FLASH
.data : AT(_etext)
{
_sdata = . ;
*(.rodata*)
*(.data)
_edata = . ;
} > RAM
data_size = _edata - _sdata ;
.bss :
{
_sbss = . ;
*(.bss)
_ebss = . ;
} > RAM
bss_size = _ebss - _sbss ;
}
Linker script
DM
IM

23. Boot .section "vectors"
_start:
j Reset_Handler
j Syscall_Handler
j Systick_Handler
Reset_Handler:
init_data:
la $r0, _etext
la $r1, _sdata
la $r2, data_size
la $r3, #0x000000FF
copy_data:
beqz $r2, init_bss
lwi.bi $r4, [$r0], #4
…
swi.bi $r4, [$r1], #4
addi $r2, $r2, #-4
j copy_data
init_bss:
la $r0, _sbss
la $r1, bss_size
zero_bss:
beqz $r1, init_sp
movi $r2, #0
swi.bi $r2, [$r0], #4
addi $r1, $r1, #-4
j zero_bss
init_sp:
la $sp, STACK_ADDR
j main
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
Reset_Handler
Syscall_Handler
Systick_Handler
Vector table
vector table
copy data section
from flash to ram
init 0 for bss section
set stack point
go C main function

24. Context switch
to_user_mode:
smw.adm $r1, [$sp], $r27, 14
movi $r1, #1
mtsr $r1, $PSW
mtsr $r1, $IPSW
addi $sp, $r0, #8
lmw.bim $r4, [$sp], $r27, 0
iret
to_kernel_mode:
mfsr $r0, $P_P1
smw.adm $r3, [$r0], $r27, 0
addi $r0, $r0, #-4
lmw.bim $r1, [$sp], $r27, 14
jr $lp
$PSW SYSTEM_MODE (RW) 0:kernelmode 1:
usermode
$IPSW IRET_MODE (RW) 0:kernelmode 1:
usermode
$P_P0 KSP (R) kernel stack point
$P_P1 USP (R) user stack point

25. Need to know
mul_u10:
slli $r1, $r0, #2
add $r0, $r1, $r0
slli $r0, $r0, #1
mod_u10:
addi $r1, $r0, #0
jal div_u10
jal mul_u10
sub $r0, $r1, $r0
unsigned div_u10(unsigned n){
q=(n>>1)+(n>>2);
q=q+(q>>4);
q=q+(q>>8);
q=q+(q>>16);
q=q>>3;
r=n-(((q<<2)+q)<<1);
return q+((r+6)>>4);
}
● No implement multiply and divison in CPU
● Compile with -O2 for using array
● Only use “int” type for all variable
● Volatile the variable for peripheral
● ISR need to put in boot.s

26. Compile Flow
.c
.s
.s _.s .o .elf .bin .prog
gcc as ld objcopy
iverilog loading
binary_analyze.pyopcode_translate.py

27. Conclusion

28. Next?
● Bugs
● Run on FPGA
● DMA, Write-back cache, ......

29. Final
● Need big screen for staring waveform
● Bugs everywhere
● Be care of using -O3
● Know more about CPU can help c programming
● Definition of HW & SW is different from EE & CS

30. Thank you.