Debugging is a challenging step for FPGA design. This presentation shows how EXOSTIV can help speed up by providing superior visibility into the chip.

1. Visibility into the FPGA.
How to capture Gigabytes
of traces from FPGA.
At speed.

2. Visibility into the FPGA.
Debugging with a JTAG solution

3. Visibility into the FPGA.

4. Visibility into the FPGA.
EXOSTIV

5. Visibility into the FPGA.

6. Visibility into the FPGA.

7. Visibility into the FPGA.
Reach internal nodes
• Up to 16 capture units
• Up to 16 data sets per CU
• 1 trigger + 1 qualification unit per CU
• Up to 2.048 nets per data set
• IP RAM does not grow with capture size
• Sampling @ system speed
Extract trace
• Up to 8 GB for trace storage
• Up to 4 x 12.5 Gbps bandwidth
• Uses Multi Gigabit Transceivers
• HDMI and SFP+ cage connector
• Optional connector adapters
• Downstream channel for IP
control
• USB 3.0 connection with
workstation
Control & Analyze
• IP configuration & insertion
• Trigger and data filter set up
• IP communication and control
• Trace reception and encoding
• Advanced waveform viewer
EXOSTIV - Overview

8. Visibility into the FPGA.
Indicative gain

9. Visibility into the FPGA.
High-speed connector – HDMI
format – up to 4 x 10 Gbps
High-speed connectors – SFP+ format – up to 4 x 12.5 Gbps
EXOSTIV Probe

10. Visibility into the FPGA.
FMC HPC / LPC
(with adapter)
Custom low footprint
Connectivity
SFP+ or QSFP+
(copper / fiber)

11. Visibility into the FPGA.
FMC / QSFP connectivity

12. Visibility into the FPGA.
Custom low footprint connectivity

13. Visibility into the FPGA.
QSFP+ connectivity

14. Visibility into the FPGA.
Choose the board you like
- Pick a standard FPGA board
• Xilinx development kits
• Intel development kits
• The Dini Group / Synopsys
• proFPGA
• High Tech Global
• Enclustra
• REFLEX CES
• …
- Use a FPGA board designed in-house
• Add a custom connector
• Use an existing connector, possibly with an adapter
(See the Connecting Guide)
https://www.exostivlabs.com/support/fpga-boards/

15. Visibility into the FPGA.
HDL
System-level
Synthesis
Debug core
insertion
Implementation
Binary load
EXOSTIV debug
EXOSTIV definition
Netlist / Automatic flow
HDL
System-level
Synthesis
Implementation
Binary load
EXOSTIV debug
EXOSTIV definition
RTL / Manual flow
IP insertion flows

16. Visibility into the FPGA.
IP Overview

17. Visibility into the FPGA.
Use EXOSTIV beyond ‘Debug’
- Extend simulation
• Real-world inputs, including rare conditions
• Improve statistical coverage / quality of sim
• Record with EXOSTIV, analyse with simulation
- Automate tasks with scripting
- Allows at speed operation
• Use the target system in a real environment
• See / Collect data for hours:
https://youtu.be/RS0kYePceME

18. Visibility into the FPGA.
EXOSTIV in the lab
• 32K nodes per FPGA max
• 8 GB memory
• 50 Gbps bandwidth
• > 350 MHz operation
• Data multiplexing, triggering, filtering, event counters
• Integrated waveform viewer
• Xilinx Series 7, Ultrascale(+), Zynq / Intel Series 10 support

19. Visibility into the FPGA.
Thank you.