Baseband processor final rev
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This is my presentation of a baseband processor, which I have developed as a major project in masters, This presentation, gives you an overview of results and effectiveness, of the processor in respect of FPGA and ASIC level.
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Baseband processor final rev
- 1. Reconfigurable Baseband Processor Presented By: Harshit Srivastava CDS12M001 Guided by: Dr Noor Mahammad SK Indian Institute of Information Technology DesignIndian Institute of Information Technology Design & Manufacturing Kancheepuram, India& Manufacturing Kancheepuram, India PROJECT REVIEW – March 2014 1Review March 2014-IIITDM 1
- 2. Outline • Introduction • Background • Motivation • Objective • Conclusion • References 2Review March 2014-IIITDM 2
- 3. Introduction • Baseband Signal: is a low pass signal whose frequency is close to zero with respect to highest frequency of the same signal • Baseband signal is a message signal with original frequency, which will be processed, • Converted • Modulated • Example: Audio signal (20Hz-20KHz) is a baseband signal, this signal is modulated to transmit as RF signal 3Review March 2014-IIITDM 3
- 4. Modulation & Need of Modulation Modulation: It is a process of mixing a signal with a sinusoid signal (carrier signal) to produce new signal of higher frequency or lower frequency which benefits during transmission. Need of Modulation: Modulation is used to transmit a baseband signal to the receiver. For e.g., let's consider a channel that essentially acts like a band-pass filter: both the lowest and highest frequency components are attenuated or unusable, with transmission only being practical over some intermediate frequency range. If we can't send low-frequency signals or vice-versa, then we need to shift our signal frequency up or down. Modulation allows us to send a signal over a band-pass frequency range. Review March 2014-IIITDM 4
- 5. Baseband Processing Elements CHANNEL CODING MODULATION SYMBOL SHAPING DACMAC LAYER ADC FILTERING DE- MODULATION FORWARD ERROR CORRECTION PATH MAC LAYER BASEBAND PROCESSOR BASEBAND TRANSMITTER BASEBAND RECEIVER Scrambler FEC Interleave r FFT Spreading Filter 5 Review March 2014-IIITDM 5
- 6. Background • The demand for high quality transmission increases, the need for increasing spectrum efficiency and improving error performance becomes important in wireless communication systems. • Many Modulation method have been designed for various channels and applications, different channel need different modulation. • Numerous wireless communication protocols have been proposed recently, each targeting a different application domain, such as WCDMA and GSM for wide area communication, WLAN for high speed, medium range communication and UWB for high speed, short distance communication 6Review March 2014-IIITDM 6
- 7. Motivation • In this wireless communication era • Data rates of the communication radios are gradually increasing • It mean the underline hardware circuitry for baseband signal processing has to be changed • Procuring a new technology based device is expensive • In this scenario the recently procured radio has to be replaced with new ones • Reconfigurable devices can be • Reconfigured as per future technology variations. • It mean hardware can be re-instructed as per our needs, when ever it is required. 7Review March 2014-IIITDM 7
- 8. Data Sequence NRZ Encoder Demux Multiplier QPSKADD ModulatorBPSK Mux Complex code chips of QPSk Differential Modulator Demux Shifter and Modulator Quad adder Dela y Phase SUM Computed DWT Extraction of Transforma tion Coefficient Histogram Matching GMSK Identified OQPSK Shift QAM dela y Y=tanx Sum Clock Clock CCK DQPSK Yes SUM ADD No. of Peaks in Histogram=1 Quadratur e Shift Pi/2 Q-OQPSK Demultiplexed F=1/T F=1/T Sin(2*pi*fc*t) Cos(2*pi*fc*t) Sin(2*pi*fc*t) Multiplier Sin(2*pi*fc*t) Cos(2*pi*fc*t) Shifter and Modulator Proposed Reconfigurable Baseband Processor frame work Block Diagram Block Diagram
- 9. Results Fig. No. BPSK and QPSK Output Fig. No. 4 : ASK and FSK Output Various Modulation schemes results Final Review December 2013-IIITDM
- 10. Results Fig. No. 4 : QAM Signal Output In Time Domain Fig.No. 5 GMSK Signal Spectrum Fig. No. 6 GMSK Resolved Signal Spectrum
- 11. What is Pipelining… • Pipelining is an implementation technique where multiple instructions are overlapped in execution. • It means in this a second instruction set can be executed before the completion of first instruction set and so on. Final Review December 2013-IIITDM
- 12. Proposed Baseband Pipelined Framework Review May 2014-IIITDM 12 Text Text Generation Control of Bits Computation I Q Stage Output stage Pairing and impairing On/off Control Main Control DeMux DeMux Mux Output/ Generator Complex Chips Generator Memory Clock MUX/ DEMUX IFFT Selection Mechanism Mux Adder Multiplier BPSK QPSK/QAM Differential CCK Shift Shifter Adder Multiplier 8PSK GMSK Shared Memory Bus Generator DataBits
- 13. Why Re-configurability with Pipelining? • Re-configurability is a hardware technique in which it can erase data and rewrite it dynamically or statically. • While pipelining is used to increase instruction set in unit of time. • With time there would be change in protocols and technology which would be targeting different application in different domain. • E.g: WCDMA and GSM for WAN communication • With pipelining we can reduce the size of the circuitry. • A system that was designed for short communication can not be used for long communication vice-versa • Due to variations in architectures • Can have different modulation/demodulation schemes • System should be not only made for today but by mere changes it can be reconfigured to newer level at future time. • Re-configurability can be structured in wireless communication baseband ,which can be seen in Modulators, scrambler, interleaver, IQ mapper etc. 13 Review March 2014-IIITDM 13
- 14. Advantages and Disadvantage of Pipelining and Reconfigurable System • Advantages: • Multiple communication protocols in a single platform. • It can performs multiple output in parallel. • It increases the instruction throughput. • Increasing number of protocols can be inserted if needed in the system at any time. • It can dynamically select the suitable baseband protocol needed for the system at particular instant. • Less no. of blocks i.e., less area would be required • Which corresponds to low power consumption. 14Review March 2014-IIITDM 14
- 15. Implementation of Proposed Framework without Pipeline • It is been implemented in stages. • The implementation is done in Verilog. • All the stages have been implemented without pipelining. • All the stages have been checked for modulation output. Review March 2014-IIITDM 15
- 16. Un-pipelined Working Design Review March 2014-IIITDM 16 Verilog un-pipeline architecture of baseband processor SelectorLine/topasdivededsignalornormal BinaryInput Data NRZ Encoder DEMULTIPLEXER Demultiplexer Even Odd Bit Divider Demultiplexer Sin(2*pi*fc*t)Cos(2*pi*fc*t) Carrier Signal Generator GMSK ASK QPSK FSK DPSK DQPSK QAM BPSK Level Shifter Level Shifter Gaussian Filter D- encoder QPSK BUFFER Memory P-QPSK DemuxChanger Q-QPSK Demux DemultiplexerforCos DELAY D- Encoder QPSK DELAY Hilbert Transfor- mation DQPSK Encoder Demux Changer 8 MHz Demux CCK 64 bit Complex Chips encoder Inverter Multipliers Adders DemultiplexerforSin
- 17. Pipeline Working Design Review March 2014-IIITDM 17 GMSKqCCKiCCK Adder QAMDQPSK ASKBPSKFSKDPSK InputData Bit EvenOdd BitDivider Sameas Input NRZ Encoder Selectorlinetoselectevenodd/oddbits/Inputbit/NRZbits STAGE1 Carrier Signal Generator Demux EvenBits NRZ output MultipliersMultipliers STAGE2 + XNORXNOR 64bit Complex Chips Generator Sin(2*pi*fc*t)Cos(2*pi*fc*t) ASKBPSKGMSKiCCKqCCK DQPS K QPSKDPSKFSKCCK OddBits Demux Level Shifter Level Shifter D- Encoder DPSK DELAY Inverter Adder Adder QPSK Memory Buffer Carrie Signals Q-QPSKP-QPSK Bits Divider andBits Offsetter Multiplier XNOR DELAY XNOR DELAY Sin(2*pi*fc*t) D-EncoderDQPSK Cos(2*pi*fc*t) Multiplier Gaussian Filter Multiplier STAGE3 1:8MultiplexerCos(2*pi*fc*t) Hilbert Transforma- tion STAGE4 + Demultiplexer + + GenerationStage ControlStage ComputationStage IQStage Outputs Sin(2*pi*fc*t)
- 19. Results Review May 2014-IIITDM 19 S. No. Modulation Scheme Output Output Stage 1 Carrier Signal Sine - 00000000101011111100000011110101 First Cosine - 00000000111111000011100010100110 First 2 ASK 0000000000000000000000000000000000101011110110101101011110101001 Second 3 BPSK 0000000000000000000000000000000000101011110001001000010111010010 Second 4 FSK 0000000000000000000000000000000011111111111111100100011011111110 Second 5 QPSK 0000000000000000000000000000000000101111011011100000110000001100 Second 6 QAM 000000000000000000000000000000000000000000000000000000010000010010000000111100011 000000001101001001000011001010100001101000000 Third 7 DQPSK 000000000000000000000000110000111110000011100011110000100000011111010010101100101 101001011000100101000011001000000000100000000 Third 8 iCCK 000000000000000000000000000111111111111111100111001111111101111100011000111111100 000000000011111001011101111011000011110110000000 Fourth 9 qCCK 000000000000000000000000011111111111111100000011110111000110100000001110011000000 10111111111100010001100011111001011001100000000 Fourth
- 20. Snapshot of Result in Xilinx Review March 2014-IIITDM 20
- 21. Individual Architectures Synthesis Results and Comparison Review March 2014-IIITDM 21 S. N. Output Time(ps) Area(µm2 ) Power(n W) 1 Carrier Signal 22338.00 209620.53 13174.38 2 ASK 951.80 5912.40 195365.99 3 BPSK 951.80 5912.40 195365.99 4 FSK 1115.90 12752.31 7441.57 5 DPSK 1052.45 3257.64 11442.63 6 QPSK 1137.20 12737.49 423060.66 7 DQPSK 8554.70 6522.74 500698.20 8 QAM 1454 13694.64 148712.83 9 CCK 8553.70 11277.25 539444.52
- 22. Review March 2014-IIITDM 22
- 23. Architecture Synthesis Results and Comparison ASIC Architecture Properties - 45nm Library Un-Pipelined Architecture Pipelined Architecture Time (psec) 24931.20 8390.10 Area (µm2 ) 287015 315139 Power (nW) 373124.07 1086681.53 Review March 2014-IIITDM 23
- 24. Conclusions • Designed the real model for stage one of proposed framework. • Analysed and designed the working procedure of the system with the help of Verilog code in Xilinx. • Got average time delay of system of about 18.46ns. • Analysed the various digital modulation schemes and its hardware implementations. 24Review March 2014-IIITDM 24
- 25. References [1] L. Tang, J. Peddersen, and S. Parameswaran, “A rapid methodology for Multi-mode communication circuit generation,” in Proceedings of the 2012 25th International Conference on VLSI Design, 2012. [2] A. Karmakar and A. Sinha, “A novel architecture of a reconfigurable radio processor For implementing different modulation schemes,” in International Conference on Computer Research and Development, 2011. [3] “Bcm4330 product brief.” Available at: www.broadcom.com. [4] K. Smitha, A. P. Vinod, and R.Mahesh, “Reconfigurable area and power efficient i-q Mapper for adaptive modulation,” in International Midwest Symposium on Circuits and Systems, 2011. [5] N. Himanshu Shekhar, C.B.Mahto, “FPGA Implementation of Tunable FFT For SDR Receiver,” in International Journal of Computer Science and Network Security, pp. 186–190, 2009. [6] Y. Lin, H. Lee, M.Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner, “Soda: A high- performance dsp architecture for software-defined Radio,” IEEE Micro, vol. 27, pp. 114–123, 2007. [7] M.I.Taj, O.Hammami, and M.Akil, “SDR waveform components Implementation on single FPGA multiprocessor platform,” in ICECS, pp. 790 –793, Dec. 2010. [8] “Multiband OFDM physical layer specification,” 2005. Available at: http://www.wimedia.org/. [9] “Official ieee 802.11 working group project timelines,” 2011. Available at: http://www.ieee802.org/11/Reports/802.11_Timelines.htm. [10] J. Proakis, Digital communications. McGraw-Hill series in electrical and Computer engineering, McGraw-Hill, 2001. 25 Review March 2014-IIITDM 25
- 26. Thank You 26Review March 2014-IIITDM 26
- 27. Backup Slides 27Review March 2014-IIITDM 27
- 28. Sub Process Working Design Line bit to Even oddLine bit to Even odd 0 0 0 By 2 Adder/Subtracter Adder Subtracter By 2 Constant BIPOPLAR Signal EVEN ODD Review March 2014-IIITDM 28
- 29. Hardware Analysis S. No. Modulation Schemes Generated No. of Blocks needed General Architecture No. of Blocks needed in Proposed Framework 1 ASK 3 3 2 FSK 9 9 3 BPSK 21 21 4 QPSK 32 5 5 QAM 43 11 6 DQPSK 39 8 7 GMSK 50 13 8 CCK 63 19 9 Total 260 79 When the proposed framework is applied, the area is reduced to 79 blocks which shows 30 % of reduction in size of the framework from normal and is 69.6 % efficient in area Final Review December 2013-IIITDMReview March 2014-IIITDM 29
- 30. Modulations Modulation Analog Amplitude SSB DSB Vestigial Quadrature Amplitude Angle FM PM Digital PSK BPSK QPSK ASK FSK QAM First review October 2013-IIITDM 30Final Review December 2013-IIITDMReview March 2014-IIITDM 30
- 31. Sub Process Working Design of Stage One ON STATE DATA I/Ps UPPER LIMIT LOWER LIMIT COMPAR- ATOR OK DECISION FALSE/STOP OFF STATE OUTPUT SUB COMPARATOR On/off Switch Review March 2014-IIITDM 31
- 32. Add and Subtract Operation Mode = 0: S = A + B, input carry = 0 Mode = 1: S = A + B’ + 1, Input carry = 1 • As – sign of A • Bs – sign of B • As & A – Accumulator • AVF – overflow bit for A+B • E – Output carry for parallel adder Review March 2014-IIITDM 32
- 33. Multiply Operation • Q – Multiplier • B – Multiplicand • A – 0 • SC – number of bits in multiplier • E – overflow bit for A • Do SC times • If low-order bit of Q is 1 • A A + B • Shift right EAQ • Product is in AQ Review March 2014-IIITDM 33