Hitachi VSP is a new paradigm in enterprise array performance. In this session we will discuss how the architecture of VSP enhances its box-wide performance. The results of performance testing with synthetic host I/O generators and the PAI/O driver will also be presented.
Streamlining Python Development: A Guide to a Modern Project Setup
Why hitachi virtual storage platform does so well in a mainframe environment webinar
1. WHY HITACHI VIRTUAL
STORAGE PLATFORM DOES
SO WELL IN A MAINFRAME
ENVIRONMENT
HOW FAST CAN A VSP GO?
RON HAWKINS, MANAGER,
TECH OPS PERFORMANCE
NOV. 2, 2011
2. WEBTECH EDUCATIONAL SERIES
Why Hitachi Virtual Storage Platform (VSP) Does So Well in a Mainframe
Environment
Hitachi VSP is a new paradigm in enterprise array performance. In this session
we will discuss how the architecture of VSP enhances its box-wide performance.
The results of performance testing with synthetic host I/O generators and the
PAI/O driver will also be presented.
Attend this WebTech to learn how to:
Improve performance in your environment with VSP
Affect performance in mainframe environments with different RAID
architectures
Optimize functionality with wide striping enabled by Hitachi Dynamic
Provisioning
3. UPCOMING WEBTECHS
November and December
‒ Increase Your IT Agility and Cost-efficiency with HDS Cloud
Solutions, Nov. 9, 9 a.m. PT, 12 p.m. ET
‒ Best Practices for Upgrading to Hitachi Device Manager
v7, Nov. 16, 9 a.m. PT, 12 p.m. ET
‒ Hitachi Clinical Repository, Dec. 7, 9 a.m. PT, 12 p.m. ET
Please check www.hds.com/webtech for
‒ Link to the recording, presentation and Q&A (available next
week)
‒ Schedule and registration for upcoming WebTech sessions
4. WE ARE TOP GUN
WHAT WE WILL COVER
Unified microprocessor
FICON front-end director
The numbers
Hitachi Dynamic
Provisioning for
Mainframe
Hitachi Virtual
Storage Platform
13. FICON FRONT-END DIRECTOR
FICON 16-PORT FEATURE
Hitachi transport processor
‒ Initial FICON protocol
‒ Open exchanges
MHUB + ASIC
‒ Data accelerator circuit
‒ A programmable
application-specific
integrated circuit
‒ Route command to virtual
storage director (VSD)
‒ Direct memory access
(DMA) engine
14. HITACHI VIRTUAL STORAGE PLATFORM
8-PORT FICON BOARD
HITACHI TRANSPORT PROCESSOR
Accepts initial channel
command request from
host
Multi-protocol
‒ FICON and high-
performance FICON
(zHPF)
Establishes open This graphic is getting
hard to read in the red.
exchanges (480) Can the type be
reversed? -th
‒ Shared on demand by
Not Really as it is a
adjacent ports graphic lifted from
another source, we
don’ t have the original
graphic.
15. OPEN EXCHANGES
HITACHI TRANSPORT PROCESSOR
64 for each host channel
‒ 2:1 fan-in is 128
‒ Adjacent ports 256 CMR
Time
‒ 4:1 fan-in is 256
‒ Adjacent ports 512
Open Exchange (OE)
exhaustion increases
Command Response (CMR)
time
‒ Microprocessor busy (>80%)
‒ Low cache hits
‒ TCz synchronous
16. HITACHI VIRTUAL STORAGE PLATFORM
8-PORT FICON BOARD
MHUB + ASIC
Two chips working
together
‒ Processor plus
programmable ASIC
‒ Commands to/from virtual
storage director
‒ Using LDEV mapping
tables
DMA engine
‒ Read and write directly to
cache
18. WE ARE TOP GUN
HITACHI UNIVERSAL STORAGE PLATFORM® V DUAL-CHASSIS CONFIGURATION
All tests are a fully popped VSP (unless stated otherwise)
‒ 2 chassis
‒ 8 virtual storage directors
‒ 4 back-end directors
‒ 16 front-end directors (128 channels)
‒ 2048 HDD (10K 300GB)
‒ 512GB cache
19. WE ARE TOP GUN
HITACHI UNIVERSAL STORAGE PLATFORM® V AS AN I/O DRIVER
FNP Driver Results
1200000
1000000
800000
600000
400000 FNP Driver Results
200000
0
Zero Zero Front End Front End
Locality Locality Write Read
Write Read
20. PAI/O TESTING
THE LAB TO THE REAL WORLD
Extended format VSAM
‒ 4KB and 26KB
High overhead
‒ Two CCW per block
Growing format for DB2
Datasets >4GB
What customers will really
get
28. WE ARE TOP GUN
HIGH-PERFORMANCE BED FEATURE
PAI/O H4
4K Read
100% Cache Miss
20
18
16
Response Time MS
14
12
10
8
6
4
2
0
0 20,000 40,000 60,000 80,000 100,000 120,000 140,000 160,000
IO Operations per Second
High Performance (2 BED) Standard Performance (1 BED)
29. WE ARE TOP GUN
HIGH-PERFORMANCE BED FEATURE
PAI/O G0 - Sequential Read
27K Chain Length 30 (1 Cyl)
100
90
80
Response Time MS
70
60
50
40
30
20
10
0
0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000
MB per second
High Performance (2 Bed) Standard Performance (1 BED)
37. UPCOMING WEBTECHS
November and December
‒ Increase Your IT Agility and Cost-efficiency with HDS Cloud
Solutions, Nov. 9, 9 a.m. PT, 12 p.m. ET
‒ Best Practices for Upgrading to Hitachi Device Manager
v7, Nov. 16, 9 a.m. PT, 12 p.m. ET
‒ Hitachi Clinical Repository, Dec. 7, 9 a.m. PT, 12 p.m. ET
Please check www.hds.com/webtech for
‒ Link to the recording, presentation and Q&A (available next
week)
‒ Schedule and registration for upcoming WebTech sessions
they build to show explain that you have to add resource in sync to maintain performance. Need to leave them in.
MHUB refers to the chip on the FED. Not sure what it means but don’t need to spell it out.
What does the asterisk after “C” in the title refer to?It is the name referring to a number of drivers that are part of the PAI/O performance testing package