The document describes the design and implementation of a seven segment counter on an FPGA. It includes the implementation of a prescaler, debouncing circuit, binary coded decimal (BCD) counter, and seven segment decoder. The prescaler was initially generating a warning about excessive skew, which was resolved by adding a clock buffer to the prescaler output. The design components are instantiated and connected in the top level system counter entity.

1. FPGA
Creating Counter
Created by
Akhmad Hendriawan
hendri@eepis-its.edu

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Created by
Akhmad Hendriawan
hendri@eepis-its.edu

4. Design system

5. Background
●I try implement counter seven segmen with
input clock from switch.
●Because push button is mechanical then I try to
remove bouncing effect with debouncing circuit

6. Problem and solution
Although I succeed to implement my design and upload to bit stream to
FPGA but there was warning with warning message “ prescaller may have
excessive skew”.

7. My first prescaller with warning
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity Prescaller is
Port ( clk_i : in STD_LOGIC;
psc_out : out STD_LOGIC);
end Prescaller;
architecture Behavioral of Prescaller is
signal clk_r: std_logic_vector(17 downto 0) := (others=>'0');
begin
process (clk_i,clk_r)
begin
if rising_edge(clk_i) then
clk_r <= clk_r+1;
end if;
end process;
psc_out<=clk_r(17);
end Behavioral;

8. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
Prescaller.vhd
Library UNISIM;
use UNISIM.vcomponents.all;
entity Prescaller is
Port ( clk_i : in STD_LOGIC;
psc_out : out STD_LOGIC);
end Prescaller;
architecture Behavioral of Prescaller is
signal clk_r: std_logic_vector(17 downto 0) := (others=>'0');
begin
process (clk_i,clk_r)
begin
Implement clock buffer to output prescaler solve
if rising_edge(clk_i) then warning error.
clk_r <= clk_r+1;
end if;
end process;
BUFG_inst : BUFG
port map (
O => psc_out, -- Clock buffer output
I => clk_r(17) -- Clock buffer input
);
end Behavioral;

9. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity debouncing is
Port ( clk_i : in STD_LOGIC;
dbin : in STD_LOGIC;
dbout : out STD_LOGIC);
end debouncing;
architecture Behavioral of debouncing is
signal Q1, Q2, Q3 : std_logic; Debouncing.vhd
begin
A: process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
Q1 <= dbin;
Q2 <= Q1;
Q3 <= Q2;
end if;
end process;
B: process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
dbout <= Q1 and Q2 and (not Q3);
end if;
end process;
end Behavioral;

10. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity counterBCD is
Port ( clk_i : in STD_LOGIC;
bcd_o : out STD_LOGIC_VECTOR (3 downto 0));
end counterBCD;
architecture Behavioral of counterBCD is
signal clk_r: std_logic_vector (3 downto 0) := (others=>'0'); Counter BCD.vhd
begin
process (clk_i)
begin
if rising_edge(clk_i) then
if(clk_r < 9) then
clk_r<= clk_r+1;
else
clk_r<= (others => '0');
end if;
end if;
end process;
bcd_o <= clk_r;
end Behavioral;

11. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
Port ( clk : in STD_LOGIC;
bcd : in STD_LOGIC_VECTOR (3 downto 0);
segment7 : out STD_LOGIC_VECTOR (6 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process (clk,bcd)
begin
if (clk'event and clk='1') then Decoder.vhd
case bcd is
--common anoda gfedcba
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;

12. library IEEE;
use IEEE.STD_LOGIC_1164.ALL; COMPONENT decoder
PORT(
entity syscnt is clk : IN std_logic;
Port ( clk_i : in STD_LOGIC; bcd : IN std_logic_vector(3 downto 0);
pb_i : in STD_LOGIC; segment7 : OUT std_logic_vector(6 downto 0)
counter_out : out STD_LOGIC_VECTOR (6 downto 0) );
); END COMPONENT;
end syscnt;
signal psc_cable: std_logic;
architecture Behavioral of syscnt is signal db_cable: std_logic;
signal bcd_o_cable: std_logic_vector(3 downto 0);
COMPONENT Prescaller
PORT( begin
clk_i : IN std_logic;
psc_out : OUT std_logic Inst_Prescaller: Prescaller PORT MAP(
); clk_i => clk_i,
END COMPONENT; psc_out => psc_cable
);
COMPONENT debouncing
PORT( Inst_debouncing: debouncing PORT MAP(
clk_i : IN std_logic; clk_i => psc_cable,
dbin : IN std_logic; dbin => pb_i,
dbout : OUT std_logic dbout => db_cable
); );
END COMPONENT;
Inst_counterBCD: counterBCD PORT MAP(
COMPONENT counterBCD clk_i => db_cable ,
PORT( bcd_o => bcd_o_cable
clk_i : IN std_logic; );
bcd_o : OUT std_logic_vector(3 downto 0)
); Inst_decoder: decoder PORT MAP(
END COMPONENT; clk => db_cable,
bcd => bcd_o_cable,
segment7 => counter_out
Syscnt.vhd );
end Behavioral;