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2. DOCUMENT FORMAT
• Abstract:
• Introduction:
• Literature Survey:
• System Analysis:
• Existing System:
• Disadvantages:
• Proposed System:
• Advantages:
• System Requirements:
• Block Diagram:
• Working Flow Diagram:
• Circuit Diagram:
• Implementation:
• Modules Description:
• System Study:
• System Testing:
• Software Description:
• Sample code:
• Conclusion:
• Future Enhancement:
• References:
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3. AN EFFICIENT CONSTANT MULTIPLIER ARCHITECTURE BASED ON
VERTICAL-HORIZONTAL BINARY COMMON SUB-EXPRESSION
ELIMINATION ALGORITHM FOR RECONFIGURABLE FIR FILTER
SYNTHESIS
TITLE
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4. ABSTRACT
This paper proposes an efficient constant multiplier architecture based on vertical-
horizontal binary common sub-expression elimination (VHBCSE) algorithm for
designing a reconfigurable finite impulse response (FIR) filter whose coefficients can
dynamically change in real time. To design an efficient reconfigurable FIR filter,
according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression
elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on
the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE
algorithm horizontally within each coefficient. This technique is capable of reducing
the average probability of use or the switching activity of the multiplier block adders by
6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms
respectively.
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