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Introducing the Vitis
Unified Software Platform
Ramine Roane
VP Software & AI Product Management
Under embargo until Oct. 1, 2019 @ 9 am Pacific, noon Eastern
Announcing…
• Available in a month
• Standards, Open
• Free!
Unified Software Platform
VITAL
VITALITY
Heterogeneous
Compute
Cloud to Edge AI Proliferation
Industry
Trends
Industry Trend: Cloud/Edge Unification
Genomics Video Analytics Healthcare Finance
Data Center 5G Autonomous Driving Security
Power efficient inference
along with traditional
software
AI Proliferation
Industry Trend: AI Proliferation
2012 2019
#DEVELOPERS
Vivado
OS and
Firmware SDK
SDSoC
(Embedded)
SDAccel, Data Center
(FaaS, Alveo)
AI Inference
Acceleration
Vitis Unified
Software Platform
Platform Transformation
Industry Trend: Heterogeneous Compute
Cache
Cache Cache
1980-2000
2x/ 1.5y
process → Dennard scaling
2000-2010
2x/ 3.5y
multithreading → Amdahl’s law
2010-2020
2x/ 10y
density → Moore’s law
SINGLE CORE MULTICORE HETEROGENEOUS ADAPTIVE
HETEROGENEOUS
Cache
Scaling from: Silicon process Architecture-aware software Software-aware architecture
AcceleratorCPU Multicore CPU Multicore CPU FPGA, ACAP
2012 2018
80
70
50
AlexNet
60
BN-AlexNet
BN-NIN
ENet
GoogLeNet
ResNet-18
VGG-16
VGG-19
ResNet-34
ResNet-50
ResNet-101
ResNet-153 ResNeXt-101
Inception v3
Inception-v4
DenseNet-264 ShuffleNet 2x
SENet-154
MobileNet v2
Top-1Accuracy(1%)
Silicon Design Cycle
Pace of AI/ML Innovation
Speed of Innovation Outpaces Silicon Cycles
Innovation Cycle
Custom Data Flow
Custom Precision
Custom Memory
APPLICATION
DOMAIN
ARCHITECTURE
Architecture Adaptability
Programmable OR Adaptable
Application Architecture
1
ASIC
ADAPTABLE (once)
COMPUTE EFFICIENCY
PROGRAMMABLE
CPU, GPU, ASSP
1
COMPUTE EFFICIENCY
1
3
3
2
2
Why Not Programmable AND Adaptable?
FPGA, ACAP
PROGRAMMABLE
COMPUTE EFFICIENCY
1
DSA2
ADAPTABLE
DSA1
2
21
Application Architecture
2
Xilinx runtime library (XRT)
Vitis target platform
Domain-specific
development
environment
Vitis core
development kit
Vitis accelerated
libraries
OpenCV
Library
BLAS
Library
Vitis AI Vitis Video
Partners
Genomics,
Data Analytics,
And moreFinance
Library
Analyzers DebuggersCompilers
Vitis: Unified Software Platform
Coming soon…
1997 2004 2009 2014 2019 2024
IBM Watson becomes
Jeopardy champion!
Image
classification
Classification
better than humans
AlphaGo beats
Lee Sedol
AlphaZero
chess champion!
ADAS
Deep Blue (traditional software)
beats Garry Kasparov
Complexity: 10^120
Robo-taxis
(geofenced) Fully
autonomous
vehicles
Deep Learning vs. Traditional Software
Announcing Vitis AI
Xilinx runtime library (XRT)
Vitis target platform
Domain-specific
development
environment
Vitis core
development kit
Vitis accelerated
libraries
OpenCV
Library
BLAS
Library
Vitis AI Vitis Video
Partners
Genomics,
Data Analytics,
And moreFinance
Library
Analyzers DebuggersCompilers
Coming soon…
Frameworks
Vitis AI
development kit
Vitis AI
models
DSA
Vitis AI: Deep Learning Acceleration
DNN Processing Unit (DPU)
Direct Framework Compilation
Minutes of Compile Times
AI Model
Quantize
Optimize
Vitis AI
Rapid Iterations from TensorFlow
Shell
Hardware
Developers
Application
Software Developers
AI Scientists
(iterations in minutes)
Embedded
Developers
Putting it All Together
Trace
if (is_uyvy) {
uyvy2bgr (in_mat, in_rgb);
}
else {
yuyv2bgr (in_mat, in_rgb);
}
resize <INTERPOLATION_AREA,
MAX_IN_HEIGHT,
MAX_IN_WIDTH,
MAX_OUT_HEIGHT,
MAX_OUT_WIDTH,
NPC,
MAX_DOWN_SCALE> (in_r, out_r);
cv.cpp
Application Example: Smart City
In Programmable Logic
AI acceleration
in AI Engine
Preprocess
Running in CPU Preprocess
Vitis Dataflow
Pipelining P
P
AI
AI
AI
Postprocess
Acceleration in
Programmable Logic
P AI Postprocess
AI
AI 6 FPS
30 FPS
40 FPS
80 FPS
Postprocess
Postprocess
In AI Engine
Adaptive Architecture for Smart City Application
Live Demo
Standard, Open
Free for Xilinx Boards
Easily Accessible Examples, Tutorials, Documentation
Extensive Open Source Libraries
Empowering Software Developers
Launching developer.xilinx.com
Easy Access to Examples, Tutorials, Documentation
Connecting developers to experts
30+ expert articles & projects and growing
Covering 9 segments
Xilinx Developer > Authors
Authors
400+ functions across 8 libraries
Open source, performance-optimized out-of-the-box acceleration
Extensive Open Source Libraries
Library
Docs
Source
Tests
Examples
Benchmarks
25 functions 12 99 114
365525 37 Models
Compilers
AI optimization
LLVM
User Since 2001
Contributor Since 2007
Now Core to Xilinx Strategy
Committed to Open Source
2007 Contributions2019
Runtime
Libraries
AI Models
20192019
Hardware Developers
Software Developers
AI & Data Scientists
Development Platforms
for ALL Developers
Unified Software Platform
Cloud to edge, software and AI
Comprehensive libraries and models
Work at Speed of Innovation
Hardware adaptable to software
Software programmable DSA
Standards, Open Source, Free
Embracing & participating in open source
Use of standard environments & APIs
Key Takeaways
Building the Adaptable,
Intelligent World
Mission

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Introducing the Vitis Unified Software Platform for Programming FPGAs

  • 1. Introducing the Vitis Unified Software Platform Ramine Roane VP Software & AI Product Management Under embargo until Oct. 1, 2019 @ 9 am Pacific, noon Eastern
  • 2. Announcing… • Available in a month • Standards, Open • Free! Unified Software Platform
  • 4. Heterogeneous Compute Cloud to Edge AI Proliferation Industry Trends
  • 6. Genomics Video Analytics Healthcare Finance Data Center 5G Autonomous Driving Security Power efficient inference along with traditional software AI Proliferation Industry Trend: AI Proliferation
  • 7. 2012 2019 #DEVELOPERS Vivado OS and Firmware SDK SDSoC (Embedded) SDAccel, Data Center (FaaS, Alveo) AI Inference Acceleration Vitis Unified Software Platform Platform Transformation
  • 8. Industry Trend: Heterogeneous Compute Cache Cache Cache 1980-2000 2x/ 1.5y process → Dennard scaling 2000-2010 2x/ 3.5y multithreading → Amdahl’s law 2010-2020 2x/ 10y density → Moore’s law SINGLE CORE MULTICORE HETEROGENEOUS ADAPTIVE HETEROGENEOUS Cache Scaling from: Silicon process Architecture-aware software Software-aware architecture AcceleratorCPU Multicore CPU Multicore CPU FPGA, ACAP
  • 9. 2012 2018 80 70 50 AlexNet 60 BN-AlexNet BN-NIN ENet GoogLeNet ResNet-18 VGG-16 VGG-19 ResNet-34 ResNet-50 ResNet-101 ResNet-153 ResNeXt-101 Inception v3 Inception-v4 DenseNet-264 ShuffleNet 2x SENet-154 MobileNet v2 Top-1Accuracy(1%) Silicon Design Cycle Pace of AI/ML Innovation Speed of Innovation Outpaces Silicon Cycles Innovation Cycle
  • 10. Custom Data Flow Custom Precision Custom Memory APPLICATION DOMAIN ARCHITECTURE Architecture Adaptability
  • 11. Programmable OR Adaptable Application Architecture 1 ASIC ADAPTABLE (once) COMPUTE EFFICIENCY PROGRAMMABLE CPU, GPU, ASSP 1 COMPUTE EFFICIENCY 1 3 3 2 2
  • 12. Why Not Programmable AND Adaptable? FPGA, ACAP PROGRAMMABLE COMPUTE EFFICIENCY 1 DSA2 ADAPTABLE DSA1 2 21 Application Architecture 2
  • 13. Xilinx runtime library (XRT) Vitis target platform Domain-specific development environment Vitis core development kit Vitis accelerated libraries OpenCV Library BLAS Library Vitis AI Vitis Video Partners Genomics, Data Analytics, And moreFinance Library Analyzers DebuggersCompilers Vitis: Unified Software Platform Coming soon…
  • 14. 1997 2004 2009 2014 2019 2024 IBM Watson becomes Jeopardy champion! Image classification Classification better than humans AlphaGo beats Lee Sedol AlphaZero chess champion! ADAS Deep Blue (traditional software) beats Garry Kasparov Complexity: 10^120 Robo-taxis (geofenced) Fully autonomous vehicles Deep Learning vs. Traditional Software
  • 15. Announcing Vitis AI Xilinx runtime library (XRT) Vitis target platform Domain-specific development environment Vitis core development kit Vitis accelerated libraries OpenCV Library BLAS Library Vitis AI Vitis Video Partners Genomics, Data Analytics, And moreFinance Library Analyzers DebuggersCompilers Coming soon…
  • 16. Frameworks Vitis AI development kit Vitis AI models DSA Vitis AI: Deep Learning Acceleration
  • 17. DNN Processing Unit (DPU) Direct Framework Compilation Minutes of Compile Times AI Model Quantize Optimize Vitis AI Rapid Iterations from TensorFlow
  • 18. Shell Hardware Developers Application Software Developers AI Scientists (iterations in minutes) Embedded Developers Putting it All Together
  • 19. Trace if (is_uyvy) { uyvy2bgr (in_mat, in_rgb); } else { yuyv2bgr (in_mat, in_rgb); } resize <INTERPOLATION_AREA, MAX_IN_HEIGHT, MAX_IN_WIDTH, MAX_OUT_HEIGHT, MAX_OUT_WIDTH, NPC, MAX_DOWN_SCALE> (in_r, out_r); cv.cpp Application Example: Smart City
  • 20. In Programmable Logic AI acceleration in AI Engine Preprocess Running in CPU Preprocess Vitis Dataflow Pipelining P P AI AI AI Postprocess Acceleration in Programmable Logic P AI Postprocess AI AI 6 FPS 30 FPS 40 FPS 80 FPS Postprocess Postprocess In AI Engine Adaptive Architecture for Smart City Application
  • 22. Standard, Open Free for Xilinx Boards Easily Accessible Examples, Tutorials, Documentation Extensive Open Source Libraries Empowering Software Developers
  • 23. Launching developer.xilinx.com Easy Access to Examples, Tutorials, Documentation Connecting developers to experts 30+ expert articles & projects and growing Covering 9 segments Xilinx Developer > Authors Authors
  • 24. 400+ functions across 8 libraries Open source, performance-optimized out-of-the-box acceleration Extensive Open Source Libraries Library Docs Source Tests Examples Benchmarks 25 functions 12 99 114 365525 37 Models
  • 25. Compilers AI optimization LLVM User Since 2001 Contributor Since 2007 Now Core to Xilinx Strategy Committed to Open Source 2007 Contributions2019 Runtime Libraries AI Models 20192019
  • 26. Hardware Developers Software Developers AI & Data Scientists Development Platforms for ALL Developers
  • 27. Unified Software Platform Cloud to edge, software and AI Comprehensive libraries and models Work at Speed of Innovation Hardware adaptable to software Software programmable DSA Standards, Open Source, Free Embracing & participating in open source Use of standard environments & APIs Key Takeaways