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Layout design on MICROWIND

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vaibhav jindal
vaibhav jindal

Basics of Layout design on MICROWIND

Engineering
1 of 56
To generate layout for CMOS Inverter circuit and simulate it for verification.
VLSI Lab VLSI LABORATORY FRONT END DESIGN (CAD) BACK END DESIGN (CAD) TECHNOLOGY (TCAD)
Proper hardware Proper software Foundry or link up with some fab lab Test facility Purpose
DESIGN STEPS • SCHEMATIC • LAYOUT DESIGN • DRC • LAYOUT Vs SCHEMATIC • PARASITIC EXTRACTION • POST LAYOUT SIMULTION
List of Experiments 1. To generate layout for CMOS Inverter circuit and simulate it for verification. 2. To prepare layout for given logic function and verify it with simulations. 3. Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool. 4. Implementation of basic logic gates and its testing. 5. Implementation of adder circuits and its testing. 6. Implementation of J-K and D Flip Flops and its testing. 7. Implementation 4 to 1 multiplexer and its testing. 8. Implementation of 3 to 8 decoder and its testing. 9. Implementation of sequential adder and its testing. 10. Implementation of BCD counter and its testing. 11. Simulation of CMOS Inverter using SPICE for transfer characteristic. 12. Simulation and verification of two input CMOS NOR gate using SPICE. 13. Introduction to Block Diagram Mathod 14. Design of digital Logic using block diagram.
Project • Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.
Design Abstraction Levels n+n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
Microwind • Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator
Tools from Microwind • Microwind • DSCH • Microwind3 Editor • Microwind 2D viewer • Microwind 3D viewer • Microwind analog simulator • Microwind tutorial on MOS devices • View of Silicon Atoms
Getting Microwind • Go to the website http://www.microwind.net/document • Download the freeware version of the microwind • Unzip the files in a Folder
Microwind Downloads
INTRODUCTION THE TOOL User-friendly and intuitive design tool for educational use. The student draws the masks of the circuit layout and performs analog simulation The tool displays the layout in 2D, static 3D and animated 3D Editing window One dot on the grid is 5 lambda, or 0.175 µm Editing icons Access to simulation 2D, 3D views Simulation properties Layout library Active technology Palette of layers Ion current Voltage cursors List of model parameters for BSIM4 Memory effect due to source capacitance Threshold voltage effect
Our Approach 1. 2. 3. 4. MOS DEVICE Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids Our approach : step-by-step illustration of the most important relationships between layout and performance. 1. Design of the MOS 2. I/V Simulation 3. 2D view 4. Time domain analysis
Feature Size • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain • Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design Rules • E.g. λ = 0.090 μm in 0.180 μm process
Layout design rules: For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.
Editing Icons Access to Simulation 2D 3D Views Layout Library Simulation Properties Palette of Layers Active Layers Current Technology Work Area One dot on the grid is 5 lambda or 0.30 µm Menu Command Microwind Environment
Microwind Layout using Verilog Code • Design Schematic in DSCH and eport Verilog code for Circuit. • Import Verilog file (.v) in microwind. • This process is possible only for digital.(As digital components are possible in Verilog)
Run on DSCH Save File Select Foundry Make Verilog File Import Verilog File LayoutVerilog File Select Foundry in Microwind DSCH to Microwind using VERILOG
Design Rules N- Well r101 Minimum width 12λ r102 Between wells 12 λ r110 Minimum well Area 144 λ2 r 102r 101 N - Well
r201 Minimum N+ and P+ diffusion width 4λ r 201 r 201 N - Well P+ Diff N+ Diff
r202 Between two P+ and N+ diffusions 4λ N - Well P+ Diff N+ Diff r 202 r 202
r203 Extra N-well after P+ diffusion 6λ N - Well P+ Diff N+ Diff r 203 r 203
r204 Between N+ diffusion and n-well 6 λ r 204 N - Well P+ Diff N+ Diff
r210 Minimum diffusion area 16λ2 r 210 r 210 N - Well P+ Diff N+ Diff
r301 Polysilicon Width 2λ N - Well P+ Diff N+ Diff Polysilicon r 301 r 301 Polysilicon
r302 Polysilicon gate on Diffusion 2λ N - Well P+ Diff N+ Diff Polysilicon r 302 r 302 Polysilicon
r307 Extra Polysilicon surrounding Diffusion 3λ N - Well P+ Diff N+ Diff Polysilicon r 307 r 307 r 307 r 307 Polysilicon
r304 Between two Polysilicon boxes 3λ N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 304 r 304
r307 Diffusion after Polysilicon 4λ N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 307 r 307 r 307 r 307
r401 Contact width 2λ Contact Polysilicon Contact Metal/Polysilicon Contact r 401
r404 Extra Poly surrounding contact 1λ Contact Polysilicon Contact Metal/Polysilicon Contact r 404 r 404
r405 Extra metal surrounding contact 1λ Contact Polysilicon Contact Metal/Polysilicon Contact r 405 r 405
N - Well P+ Diff N+ Diff Polysilicon Polysilicon r403 Extra diffusion surrounding contact 1λ r 403 r 403
Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 r 501 r 501 r501 Between two Metals 4λ
r510 Minimum Metal area 16λ2 r 510 r 510 r 510r 510 r 510 r 510 Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6
Step 1: Select Foundary
Step 2: Select Foundary
Step 3: n+ Diffussion
Step 4: Polysilicon
Step 5: n+diff and Metal Contact
• This Completes nMOS design • Now go for pMOS Design, and the first need is to construct N Well
Step 6: Create N Well
Step 6: p+ Diffusion
Step 7: Polysilicon
Step 8: Contacts
Final Connections • pMOS Completed • Now Interconnection of pMOS and nMOS to complete inverter • Connect Source of pMOS to VDD and Source of nMOS to VSS. • Short the Drain of both pMOS and nMOS.
INVERTER: Complete Design
Check DRC
Assign Source • Assign Signal (Clock) to Gate Terminal • Add Visible node at Output
Inverter with Source
Run Simulation
VTC Characteristics
For Analog Circuits (R, L and C Components) if drain and gate is shorted then MOS will behave as a diode connected load and it will never go to triode region and can be used as resistive load offering a resistance equal to 1/gm. if drain and source is shorted then MOS capacitor in which SiO2 will behave as insulator.
Direct layout design of Analog Circuits…
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Layout design on MICROWIND

  • 1. To generate layout for CMOS Inverter circuit and simulate it for verification.
  • 2. VLSI Lab VLSI LABORATORY FRONT END DESIGN (CAD) BACK END DESIGN (CAD) TECHNOLOGY (TCAD)
  • 3. Proper hardware Proper software Foundry or link up with some fab lab Test facility Purpose
  • 4. DESIGN STEPS • SCHEMATIC • LAYOUT DESIGN • DRC • LAYOUT Vs SCHEMATIC • PARASITIC EXTRACTION • POST LAYOUT SIMULTION
  • 5. List of Experiments 1. To generate layout for CMOS Inverter circuit and simulate it for verification. 2. To prepare layout for given logic function and verify it with simulations. 3. Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool. 4. Implementation of basic logic gates and its testing. 5. Implementation of adder circuits and its testing. 6. Implementation of J-K and D Flip Flops and its testing. 7. Implementation 4 to 1 multiplexer and its testing. 8. Implementation of 3 to 8 decoder and its testing. 9. Implementation of sequential adder and its testing. 10. Implementation of BCD counter and its testing. 11. Simulation of CMOS Inverter using SPICE for transfer characteristic. 12. Simulation and verification of two input CMOS NOR gate using SPICE. 13. Introduction to Block Diagram Mathod 14. Design of digital Logic using block diagram.
  • 6. Project • Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.
  • 8. Microwind • Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator
  • 9. Tools from Microwind • Microwind • DSCH • Microwind3 Editor • Microwind 2D viewer • Microwind 3D viewer • Microwind analog simulator • Microwind tutorial on MOS devices • View of Silicon Atoms
  • 10. Getting Microwind • Go to the website http://www.microwind.net/document • Download the freeware version of the microwind • Unzip the files in a Folder
  • 12. INTRODUCTION THE TOOL User-friendly and intuitive design tool for educational use. The student draws the masks of the circuit layout and performs analog simulation The tool displays the layout in 2D, static 3D and animated 3D Editing window One dot on the grid is 5 lambda, or 0.175 µm Editing icons Access to simulation 2D, 3D views Simulation properties Layout library Active technology Palette of layers Ion current Voltage cursors List of model parameters for BSIM4 Memory effect due to source capacitance Threshold voltage effect
  • 13. Our Approach 1. 2. 3. 4. MOS DEVICE Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids Our approach : step-by-step illustration of the most important relationships between layout and performance. 1. Design of the MOS 2. I/V Simulation 3. 2D view 4. Time domain analysis
  • 14. Feature Size • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain • Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design Rules • E.g. λ = 0.090 μm in 0.180 μm process
  • 15. Layout design rules: For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.
  • 16. Editing Icons Access to Simulation 2D 3D Views Layout Library Simulation Properties Palette of Layers Active Layers Current Technology Work Area One dot on the grid is 5 lambda or 0.30 µm Menu Command Microwind Environment
  • 17. Microwind Layout using Verilog Code • Design Schematic in DSCH and eport Verilog code for Circuit. • Import Verilog file (.v) in microwind. • This process is possible only for digital.(As digital components are possible in Verilog)
  • 18. Run on DSCH Save File Select Foundry Make Verilog File Import Verilog File LayoutVerilog File Select Foundry in Microwind DSCH to Microwind using VERILOG
  • 19. Design Rules N- Well r101 Minimum width 12λ r102 Between wells 12 λ r110 Minimum well Area 144 λ2 r 102r 101 N - Well
  • 20. r201 Minimum N+ and P+ diffusion width 4λ r 201 r 201 N - Well P+ Diff N+ Diff
  • 21. r202 Between two P+ and N+ diffusions 4λ N - Well P+ Diff N+ Diff r 202 r 202
  • 22. r203 Extra N-well after P+ diffusion 6λ N - Well P+ Diff N+ Diff r 203 r 203
  • 23. r204 Between N+ diffusion and n-well 6 λ r 204 N - Well P+ Diff N+ Diff
  • 24. r210 Minimum diffusion area 16λ2 r 210 r 210 N - Well P+ Diff N+ Diff
  • 25. r301 Polysilicon Width 2λ N - Well P+ Diff N+ Diff Polysilicon r 301 r 301 Polysilicon
  • 26. r302 Polysilicon gate on Diffusion 2λ N - Well P+ Diff N+ Diff Polysilicon r 302 r 302 Polysilicon
  • 27. r307 Extra Polysilicon surrounding Diffusion 3λ N - Well P+ Diff N+ Diff Polysilicon r 307 r 307 r 307 r 307 Polysilicon
  • 28. r304 Between two Polysilicon boxes 3λ N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 304 r 304
  • 29. r307 Diffusion after Polysilicon 4λ N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 307 r 307 r 307 r 307
  • 30. r401 Contact width 2λ Contact Polysilicon Contact Metal/Polysilicon Contact r 401
  • 31. r404 Extra Poly surrounding contact 1λ Contact Polysilicon Contact Metal/Polysilicon Contact r 404 r 404
  • 32. r405 Extra metal surrounding contact 1λ Contact Polysilicon Contact Metal/Polysilicon Contact r 405 r 405
  • 33. N - Well P+ Diff N+ Diff Polysilicon Polysilicon r403 Extra diffusion surrounding contact 1λ r 403 r 403
  • 34. Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 r 501 r 501 r501 Between two Metals 4λ
  • 35. r510 Minimum Metal area 16λ2 r 510 r 510 r 510r 510 r 510 r 510 Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6
  • 36. Step 1: Select Foundary
  • 37. Step 2: Select Foundary
  • 38. Step 3: n+ Diffussion
  • 40. Step 5: n+diff and Metal Contact
  • 41. • This Completes nMOS design • Now go for pMOS Design, and the first need is to construct N Well
  • 42. Step 6: Create N Well
  • 43. Step 6: p+ Diffusion
  • 46. Final Connections • pMOS Completed • Now Interconnection of pMOS and nMOS to complete inverter • Connect Source of pMOS to VDD and Source of nMOS to VSS. • Short the Drain of both pMOS and nMOS.
  • 49. Assign Source • Assign Signal (Clock) to Gate Terminal • Add Visible node at Output
  • 53. For Analog Circuits (R, L and C Components) if drain and gate is shorted then MOS will behave as a diode connected load and it will never go to triode region and can be used as resistive load offering a resistance equal to 1/gm. if drain and source is shorted then MOS capacitor in which SiO2 will behave as insulator.
  • 54.
  • 55. Direct layout design of Analog Circuits…
  • 56. Thanks Give Your Feedbacks at: www.amitdegada.weebly.com/blog.html

Editor's Notes

  1. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  2. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  3. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  4. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  5. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  6. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  7. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  8. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  9. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  10. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  11. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  12. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  13. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  14. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  15. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  16. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  17. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  18. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  19. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  20. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  21. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  22. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  23. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  24. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  25. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  26. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  27. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  28. When Drain and gate are short mosfet is in saturation.
  29. References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.