High Level FPGA Modeling for Image Processing Using Xilinx System Generator

1. BY
S.Narendra Achari
[M.TECH-I SEM]
VLSI- SD
DEPARTMENTOF ELECTRONICSAND COMMUNICATION ENGINEERING
ANNAMACHARYAINSTITUTEOFTECHNOLOGY AND SCIENCES::RAJAMPET
(AN AUTONOMOUSINSTITUTION
High Level FPGA Modeling for Image Processing Using Xilinx SystemGenerator
A TECHNICAL SEMINAR ON
H.NO:14701D5706

2. OBJECT:

3. CONTENT: INTRODUCTION
IMAGE PROCESSING
WITH XILINX
SYSTEM
GENERATOR
OPERATION
CONCLUSION

4. XILINX SYSTEM GENERATOR:
synthesis
mapping
place and route
System generator can perform
the FPGA implementation steps:

5. Model system generator within simulink

6. IMAGE PROCESSING WITH XILINX SYSTEM GENERATOR:
Image processing task using Xilinx System Generator needs two Software tools:
MATLAB
Xilinx ISE 14.1.
Design flow for Xilinx System Generator

7. HARDWARE IMPLEMENTATION OF IMAGE PROCESSING
METHOD:
Design flow of hardware implementation of image processing

8. Image Pre-Processing Unit:
Convert 2-D to 1-D: Converts the image into single array of pixels.
Frame conversion and buffer: It helps in setting sampling mode and buffering of data.
Image Pre-processing unit

9. Image Post-Processing Unit :
Convert 1D to 2D: Convert 1D image signal to 2D image matrix.
Video viewer: It is used to display the output image back on the monitor.
Image Post processing unit

10. OPERATIONS:
IN Matlab this operation can be obtained by XOR function block or simple Inverter
block
Image Negative using XOR Operations:
Image Negative using XOR Block XSG

11. RESULTS:
Input Image Input Imageoutput Image output Image
Results for Grayscale Image Negative Results for color Image Negative

12. image Negative using NOT Operations:
Image Negative using NOT Block XSG

13. RESULTS:
Input Image output image input image output image
Results for color Image Negative Results for Grayscale Image Negative

14. Image Enhancement :
image can be enhanced by adding a constant to each pixel values.
Image filtering can also be done using model based design different filtering architecture can be defined and
Xilinx block can be created.
Grayscale Image Enhancement

15. Color Image Enhancement :

16. RESULTS:
Grayscale Image Enhancement
Input Image output image input image output image
color Image Enhancement

17. Image Contrast stretching:
New pixel = 3 (old pixel-5) + 2
IMAGE CONTRAST STRETCHING

18. RESULTS:
Input Image output image input image output image
color Image Contrast stretchingGrayscale Image Contrast stretching

19. HARDWARE CO-SIMULATION:
The FPGA part to be used (virtex5 xupv5-lx110t).
Hardware co-simulation block
Synthesis tool: Specifies the tool to be used to synthesize the design.
Hardware Description Language: Specifies the HDL language to be used for compilation i. e Verilog.
Create test bench: This instructs System Generator to create a HDL test bench.
Design is synthesized and implemented.

20. Clocking Tab
FPGA clock period(ns): Defines the period in nanoseconds of the system clock
Clock pin location: Defines the pin location for the hardware clock.
Invoking the Code Generator
The code generator is invoked by pressing the Generate button
in the System Generator token dialog box.

21. CONCLUSION:
 A real-time image processing algorithms are implemented on FPGA.
 Modeling, simulation and synthesis have made FPGA a highly useful platform.
The Xilinx System Generator tool is a new application in image processing
because processing units are designed by blocks.