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1. DIGITAL MULTIPLIER
Internal Guide
T.Sireesha
Coordinator
I.V.S Rama Sastry
AEC
BHONGIR

2. OUTLINE
ABSTRACT
Booth Multiplier INTRODUCTION
EXAMPLE
BLOCK DIAGRAM
(FLOW CHART)
CODING
RESULT
CONCLUSION
VHDL LANGUAGE
ALGORITHM

3. ABSTRACT
Booth algorithm is used for Simulation and Development of Digital Multiplier. It is
a powerful algorithm for signed-number multiplication, which treats both positive
and negative numbers uniformly.
1. Thorough study an evaluating techniques for implementing digital
multiplier(BA).
2. The implementation of this algorithm is required to be carried on
FPGA using VHDL
3. Simulation of digital multiplier is to be carried out using ISIM
simulator.
4. The algorithm is required to be tested and validated on a suitable
FPGA based hardware platform which is capable of handling

5. Multipliers plays key components for many high performance
systems such as
a) FIR Filters
b) Microprocessors
c) Digital Signal Processors, etc.
With advances in technology, many researchers have tried and are trying to
design multipliers which offer either of the following design targets
i. High speed
ii. Low power consumption
iii. Regularity of layout
iv. Less area.
Or even combination of them in one multiplier thus making them
suitable for various high speed, low power and compact VLSI
implementation.

6. • There are many types of multipliers. For example:
• Array multiplier
• Serial multiplier
• Shift and Add multiplier
• Wallace tree multiplier
• Baugh Woolley multiplier
• Braun multiplier, etc.

7. Andrew Donald Booth

8.  Booth’s multiplication algorithm is the multiplication algorithm that
multiplies two signed binary numbers in two's complement form.
 The algorithm was invented by Andrew Donald Booth in 1951 while doing
research on crystallography in London.
 Booth used desk calculators that were faster at shifting than adding and
created the algorithm to increase their speed.
 Booth algorithm uses a small number of additions and shift operations to do
the work of multiplication.
 It is a powerful algorithm for signed-number multiplication which treats both:
 Positive numbers
 Negative numbers
 Booth algorithm is a method that will reduce the number of multiplicand
multiples.
Uniformly

9. BOOTH MULTIPLIER
 Registers used by Booth’s algorithm.

10. Booth’s
Multiplier
Input a
Input b
Output c

11. STEP 1:
• Decide which operand will be the
multiplier and which will be the
multiplicand.
• Initialize the remaining registers to ‘0’.
• Initialize Count Register with the number
of Multiplicand Bits.
 For Example:
 Multiplicand= 7 0111 M
 Multiplier = 3 0011 Q
 Register ‘A’ = 0 0000 A
 Register = 0 0000
 Register Count = 4 0100
Count
START
A 0 ; Q -1
0
MMultiplicand
Q Multiplier
Countn
Q-1 Q-1

12. STEP 1:
• Use the LSB (least significant bit) and
the previous LSB to determine the
arithmetic action.
• If it is the FIRST pass, use 0 as the
previous LSB.
START
A 0 ; Q -1
0
MMultiplicand
Q Multiplier
Countn
Q 0 ,Q -
1

13. STEP 2:
• Possible arithmetic actions:
• 00  no arithmetic operation
• 11  no arithmetic operation
• 01  add multiplicand to left half of
product
• 10  subtract multiplicand from left half of
product
START
A 0 ; Q -1
0
MMultiplicand
Q Multiplier
Countn
Q 0 ,Q -
1
=01
AA-M A A+M
=1
1
=0
0
=10

14. STEP 3:
• Perform an arithmetic right shift (ASR) on the
entire product.
START
A 0 ; Q -1
0
MMultiplicand
Q Multiplier
Countn
Q 0 ,Q -
1
=01
AA-M A A+M
=1
1
=0
0
=10
Arithmetic Shift right
A, Q, Q-1
Count Count -1

15. START
A 0 ; Q -1
0
MMultiplicand
Q Multiplier
Countn
Q 0 ,Q -
1
=01
AA-M A A+M
=1
1
=0
0
=10
Arithmetic Shift right
A, Q, Q-1
Count Count -1
Count
=0?
END
N0 Yes
STEP 4:
• When Count register is not ‘0’ then
continue the multiplication.
• If Count register is ‘0’ then END the
Algorithm.

16. • (7) 0111 M
• (3) 0011 Q
• (-7)1001 -M
• 0A
• 0
Q-1
• Count=no. of bits4
0 0 0 0
1 0 0 1
1 0 0 1
A
-M
A

17. EXAMPLE
BIN

18. BIN

19. 0 1 0 1
0 1 1 1
0 0 1 0
A
M
A

20. BIN

21. A Q Q-1 Action Count
0 0 0 0 0 0 1 1 0 Initial 4
1 0 0 1 0 0 1 1 0 AA-M
1 1 0 0 1 0 0 1 1 Shift 3
1 1 1 0 0 1 0 0 1 Shift 2
0 1 0 1 0 1 0 0 1 AA+M
0 0 1 0 1 0 1 0 0 Shift 1
0 0 0 1 0 1 0 1 0 Shift 0
Step
1
2
2
3
4
4
5
BIN

23. VHDL HIERARCHY

24. VHDL PACKAGES
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_signed.all;
Use ieee.std_logic_unsigned.all;

25. VHDL ENTITY
 entity my_ckt is
port (
A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit
);
end my_ckt;
Datatypes:
 In-built
 User-defined
my_ckt
A
B
S
X
Y
    Example.
  Port names or
Signal names
 Name of the circuit
 User-defined
 Filename same as circuit
name
recommended
 Example:
 Circuit name: my_ckt
 Filename: my_ckt.vhd
Direction of port
3 main types:
 in: Input
 out: Output
 inout: Bidirectional
Note the absence of semicolon
“;” at the end of the last signal
and the presence at the end of
the closing bracket

26. VHDL ARCHITECTURE
 Defines functionality of the chip
Example:
 X <= A AND B;
 Y <= C AND D;
 E <= X OR Y;
Chip A
B
C
D
X E
Y

27. DIFFERENT TYPES OF MODELING
DATAFLOW
MODELING
STRUCTURAL
MODELING
BEHAVIORAL
MODELING
MIXED
MODELING

28. DATAFLOW MODELING
 A dataflow modeling specifies the functionality of the entity without
explicitly specifying its structure.
 This functionality shows the flow of information through the entity, which
is expressed using concurrent signal assignment statements.
 An architecture body can contain any number of concurrent signal
assignment statements.
 Conditional statement can also be used in dataflow modeling.
e.g. ‘WHEN’ conditional statement.
 Dataflow modeling is used when the user knows the exact expressions
for the desired outputs.

29. STRUCTURAL MODELING
• In structural style of modeling, the entity is described as a set of interconnected
components.
• The component instantiation statement is the primary mechanism used for
describing such a model of an entity.
• Implicit definition of I/O relationship is done through particular structure.
• There is no need of sequential or conditional statements in this type of
modeling.
• A list of components and there connections in any language is used in this type
of modeling which is also sometimes called net list.
• The behavior of the entity is not explicitly apparent from its model

30. Behavioral MODELLING
 The behavioral modeling specifies the behavior of an entity as a set of
statements that are executed sequentially in the specified order.
 This set of sequential statements , which are specified inside a process
statement , do not explicitly specify the structure of the entity but merely its
functionality.
 Behavioral code cannot be written without a process statement.
 A process statement is a concurrent statement that can appear within an
architecture body. Architecture body can have any number of processes .
 A process statement also has declarative part (before the keyword begin)
and a statement part (between the keywords begin and end process ).
 The statements appearing within the process statement are sequential
statements and executed sequentially.

31. MIXED MODELING
 It is possible to mix the three modeling styles that we have seen so far in a
single architecture body.
 Within an architecture body , we can use :-
component instantiation statements( that represent structure ),
concurrent signal assignment (that represent dataflow) and
process statements (that represent behavior).
ADVANTAGES OF Behavioral MODELING:
 Code become easier for complex design.
 Code can be written block wise..
 Sequential or conditional statements can be used.
 Less time consuming.

34. TEST BENCHES

38. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Booth_Con_RCI is
Port ( X : in STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : in STD_LOGIC_VECTOR(3 DOWNTO 0);
Z : out STD_LOGIC_VECTOR(7 DOWNTO 0) );
end Booth_Con_RCI;

39. architecture Behavioral of Booth_Con_RCI is
SIGNAL A:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL S:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P1,P1_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P2,P2_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P3,P3_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P4,P4_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL P5,P5_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);
Signals can only be
defined in this place
before the begin keyword

40. begin
A(8 DOWNTO 5)<=X;
A(4 DOWNTO 0)<=(OTHERS=>'0');
S(8 DOWNTO 5)<=NOT X + "0001";
S(4 DOWNTO 0)<=(OTHERS=>'0');
P(8 DOWNTO 5)<=(OTHERS=>'0');
P(4 DOWNTO 1)<=Y;
P(0)<='0';
P1<=P WHEN (P(1 DOWNTO 0)="00" OR P(1 DOWNTO 0)="11")ELSE
P+A WHEN P(1 DOWNTO 0)="01"ELSE
P+S WHEN P(1 DOWNTO 0)="10";
P1_SHIFT(7 DOWNTO 0)<=P1(8 DOWNTO 1);
P1_SHIFT(8)<=P1(8); BIN

41. P2<=P1_SHIFT WHEN (P1_SHIFT(1 DOWNTO 0)="00" OR P1_SHIFT(1 DOWNTO 0)="11")ELSE
P1_SHIFT+A WHEN P1_SHIFT(1 DOWNTO 0)="01"ELSE
P1_SHIFT+S WHEN P1_SHIFT(1 DOWNTO 0)="10";
P2_SHIFT(7 DOWNTO 0)<=P2(8 DOWNTO 1);
P2_SHIFT(8)<=P2(8);
P3<=P2_SHIFT WHEN (P2_SHIFT(1 DOWNTO 0)="00" OR P2_SHIFT(1 DOWNTO 0)="11")ELSE
P2_SHIFT+A WHEN P2_SHIFT(1 DOWNTO 0)="01"ELSE
P2_SHIFT+S WHEN P2_SHIFT(1 DOWNTO 0)="10";
P3_SHIFT(7 DOWNTO 0)<=P3(8 DOWNTO 1);
P3_SHIFT(8)<=P3(8);
BIN BIN
P2<=P1_SHIFT
P2

42. P4<=P3_SHIFT WHEN (P3_SHIFT(1 DOWNTO 0)="00" OR P3_SHIFT(1 DOWNTO 0)="11")ELSE
P3_SHIFT+A WHEN P3_SHIFT(1 DOWNTO 0)="01"ELSE
P3_SHIFT+S WHEN P3_SHIFT(1 DOWNTO 0)="10";
P4_SHIFT(7 DOWNTO 0)<=P4(8 DOWNTO 1);
P4_SHIFT(8)<=P4(8);
Z<=P4_SHIFT(8 DOWNTO 1);
end Behavioral;
BIN

45. DESIGN SUMMARY

51. TEST BENCH ISIM
VALID
INPUTS
VALID
OUTPUTS

53. • Our project gives a clear concept of multipliers and their
implementation.
• Booth Multipliers are implemented, the complete process of the
implementation.
• As compared to Radix-2 Booth Multiplier, Radix-4 gives higher speed
and Circuit Complexity is also less.
• Secondarily, this thesis has shown that algorithms based upon the
Booth partial product method are distinctly superior in power and area
when compared to non-Booth encoded method.
• Reducing the number of partial product and creating efficient ways of
driving the long wires needed in controlling and providing multiples to
the partial product generators are areas where further work may prove
fruitful.