3. In Verilog, testbench code and design code are in a separate
module
— Much effort is required to set the environment to be properly initialized and
synchronized
To avoid race conditions between the design and testbench
SystemVerilog introduces the program block to separate the
testbench
Connections between the blocks increases as the design grows
— Any wrong connection stops the design from working
SystemVerilog also introduces the interface construct to
encapsulate the communication between design and verification
blocks
SystemVerilog Verification Building Blocks
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5. The communication between blocks
of a digital system is a critical
— Manually connecting many ports can lead
to errors
— Port declaration in many modules
— Change in the design makes it difficult to
change
SystemVerilog adds a powerful
feature called interface
Interface encapsulates the
interconnection and communication
between blocks
Interface
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6. An interface port declaration
syntax is the same as that of
modules
An interface can contain
subroutines
An interface can also contain
processes (i.e., initial or always
procedures) and continuous
assignments
This allows the interface to include
a verifier such as its own protocol
checker that automatically verifies
all modules connected via the
interface to conform to the
specified protocol
Interface Syntax
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9. In the previous example, if the same identifier u_if had been used
to name the uart_if interface in the uart_rx and uart_rx_ctl module
headers
— Then implicit port connections could also have been used to instantiate the
uart_rx and uart_rx_ctl modules into the top module, as follows
Interface Example: Implicit Port Connections
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10. To specify the direction of the signal that uses an interface instead
of a port list
— modports are used
To restrict interface access within a module, modport lists the
directions declared within the interface
Modports
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12. Usually a testbench contains the following functionality
— Interconnect instances
— Drives clocks, resets, and other control signals with some of them tied to
constant values
— Controls test duration
— Drives DUT test
Drives design inputs
Checks design outputs
Collects test statistics
All these cause the testbench to be a huge text file, containing
hundreds or thousands of lines of code
Testbenches
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13. Programs are intended to be instantiated or nested within a
testbench, encapsulating all design verification functionality
Testbench can include one or more programs
— Each program is a design verification (or sub-environment) entry-point
— Each program can call the $exit() method
When the $exit() method is called, all the threads opened within the program are
terminated
— When all the programs are done (either by calling the $exit() method or by
finishing all the threads), the $finish() system task is called automatically
Programs cannot instantiate modules, but they may have input,
output, and inout ports and interfaces like modules
Programs
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14. Program block construct is provided for modeling the testbench
environment
The program construct serves as a clear separator between
design and testbench
A program block can contain
— Data declarations, class definitions, subroutines, and one or more initial and
final procedures
A program block cannot contain
— always procedures, primitive instances, module instances, interface
instances, or other program instances
Program Syntax
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18. A clocking block is a synchronization part within a module's
interconnection (interfaces) or signal drivers (programs and
modules)
It is intended to make sequenced signals driving/sampling easier
Provides immediate ability to specify sampling signal and its input
and output skew (timing spec)
— Input skew specifies how long before a "real" clock-edge signal is sampled
— Output skew specifies how long after a "real" clock-edge signal is driven
Clocking Block
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20. Any signal in a clocking block can be associated with an arbitrary
hierarchical expression. A hierarchical expression is introduced
by appending an equal sign (=) followed by the hierarchical
expression
Hierarchical expressions are not limited to simple names or
signals in other scopes
Clocking Block Syntax (2)
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21. One clocking block can be specified as the default for all cycle
operations
A default is valid only within the scope of the default clocking
specification
Only one default clocking can be specified in a module, interface,
program, or checker
The ## operator can be used to delay execution by a specified by
number of clock cycles or clocking events
Default Clocking and ## Cycle Delay
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23. Clocking block within interface is used to specify both signal direction
(input, output or inout) and timing spec of signal sampling
Clocking block is true hierarchical construct. To access clocked signal
use hierarchical path including clocking itself
Clocking Block within Interfaces
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24. A bind operator is intended to insert a module, program, or
interface to another module or module instance
It allows the verification engineer to add design verification
utilities to design with no real RTL code changes
Bind Operator (1)
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33. Identifiers declared within a module, interface, program, or checker are
local to that scope
— Do not affect or conflict with declarations in other building blocks
SystemVerilog packages provide an additional mechanism to share with
other building blocks
Packages
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35. 1.What is the purpose of using a program block?
2.What is the need for SystemVerilog interface construct?
3.What is the purpose of clocking block?
Answer the following questions
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36. SystemVerilog verification building blocks are the program block,
interfaces, clocking block, and packages
SystemVerilog introduces the program block to separate the
testbench and to avoid the race conditions between the design
and testbench
The interface construct encapsulates the interconnection and
communication between blocks
To restrict the interface access within a module, modport lists the
directions declared within the interface
Clocking block is a synchronization part within a module's
interconnection (interface) or signal drivers (programs and
modules)
Summary
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