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Choosing the Right Processor for your Application www.pantechsolutions.net
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]
Choosing the right Processor
Microprocessor  Basic Microprocessor, by-itself, completely useless – must have external peripherals to Interact with outside world CPU CONTROL ADDRESS DATA BOOT ROM Used at  startup Instruction (program) ROM Transducers Keyboard Screen UART Parallel interface etc Data RAM
Micro controller CPU
Von  Neumann VS Harvard Von Neumann Harvard CPU 12 14 16 Memory (Data) 8 Memory (Program) CPU Memory (Program &Data)
Why do we need DSP Processor?
CPLD Vs FPGA
CPLD Vs FPGA ,[object Object],[object Object],[object Object],[object Object],[object Object]
CPLD Architecture ,[object Object],[object Object],[object Object],[object Object]
FPGA Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FPGA Technologies
Why HDL? ,[object Object],[object Object],[object Object],[object Object],[object Object]
Verilog Vs VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DSP Vs FPGA
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],When to use DSP in FPGA
Traditional embedded system design using DSP Power Supply CLK CLK CLK custom IF-logic SDRAM SDRAM SRAM SRAM SRAM Memory Controller UART LC Display Controller Interrupt Controller Timer Audio Codec CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC
Next Step... CLK custom IF-logic Memory Controller UART Display Controller Timer CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC Interrupt Controller FPGA CLK CLK SDRAM SDRAM SRAM SRAM SRAM Power Supply LC Audio Codec
Configurable system on Chip-CSoC Power Supply SDRAM SDRAM SRAM SRAM SRAM LC Audio Codec EPROM
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Multicore Processor
SMP-BF561 • Identical Cores • Identical access to all System Resources • Memory, Disk, UARTs, Communication Controllers, • Examples: Analog Devices Blackfin 561
AMP-TI OMAP ,[object Object],[object Object],[object Object]
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Selection of packages QFP SOLDERING IRON SOLDERING STATION OVEN DIP SOIC BGA PLCC
Hardware Design Flow SCHEMATIC DESIGN LAYOUT  DESIGN ASSEMBLY & TESTING
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]
Software  Design Flow
Software Design Flow -FPGA Generate Netlist ISE Platform Ext. Proj.Nav. / VHDL *.mhs *. elf *.c *.asm Compile & Link Update Bitstream *. bit *.h Gen. Libs Platform Definition (peripherals, configuration, connectivity, address space)    EDK:   Embedded Development Kit    XPS:   Xilinx Platform Studio    ISE:   Integrated Software Environment    MHS:   Microprocessor Hardware Specification *. bit XPS Generate Bitstream *.ucf Hardware Software *.bmm
RTOS, Board Support Package Integrated HW/SW/FPGA Flows Instantiate the  ‘ System Netlist’  and Implement  the FPGA Include the BSP and Compile the Software Image 1 2 3 Xilinx Platform Studio SDK Xilinx Platform Studio Data2MEM  Download Combined Image to FPGA Compiled ELF  Compiled BIT Embedded Development Kit  ? HDL Entry Simulation/Synthesis Implementation Download Bitstream Into FPGA Chipscope Standard FPGA HW Development Flow VHDL or Verilog System Netlist ? Code Entry C/C++ Cross Compiler Linker Load Software Into FLASH Debugger Standard Embedded SW Development Flow C Code Board Support Package Compiled BIT Compiled ELF
FPGA  Design Flow
Design Compilation Simulation Verification Graphical   Entry   HDL   Entry   Compiler   Timing Diagram Timing Analysis   Program CPLD   Development Board FPGA  Design Flow
Unified Tool Releases, All Tools Available for Evaluations Verilog  VHDL C/C++  MATLAB  Simulink  3 rd  Party Unified Design Environment   The Ultimate System Integration Design Tools New ! HW Designers SW Developers Architects Verification Team System Integrators . . . .
Design Decision in Choosing an FPGA  Programmable technology Gate count Number of I/O’S Manufacturer Family Device Power Consumption Speed,voltage  Packaging
Processor selection Criteria ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SW DEVELOPMENT HW DEVELOPMENT SW SELECTION HW SELECTION INTEGRATION TESTING & TUNING DEPLOYMENT Compiler RTOSs Networking Protocols Java Support Graphics Support Project & Code Mgmt. RTOS Simulation Rapid Prototyping Real-time Data Visualization  Memory Leak Detection CPU Profiling Post-mortem Debug Semiconductor Co-funded Development Hardware Coverage Board Bring-Up Board Diagnostics & Manufacturing Test Source-level Debugging  Real-time System Analysis & Triggering Execution Tracing Code Coverage Analysis In-field Debugging © 2008 Pantech Solutions™ | All rights reserved Embedded Development using FPGA
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]
Simulation Evaluation Emulation
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]
Recap of Designing an Embedded System
http://nptel.iitm.ac.in/videocourselist.php http://youtube.com/iit Website  and Resources
http://www.esacademy.com/ 8051 (Philips Flash ISP software) http://www.keil.com/demo/ Evaluation version for 8051  and  ARM http://www.microchip.com PIC FPGA http://www.xilinx.com/support/download/index.htm https://www.altera.com/support/software/download/sof-download_center.html http://www.analog.com/en/embedded-processing-dsp/content/blackfin_bold_training/fca.html DSP www.ti.com/
Questions ?
 

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Choosing the right processor

  • 1. Choosing the Right Processor for your Application www.pantechsolutions.net
  • 2.
  • 3. Choosing the right Processor
  • 4. Microprocessor Basic Microprocessor, by-itself, completely useless – must have external peripherals to Interact with outside world CPU CONTROL ADDRESS DATA BOOT ROM Used at startup Instruction (program) ROM Transducers Keyboard Screen UART Parallel interface etc Data RAM
  • 6. Von Neumann VS Harvard Von Neumann Harvard CPU 12 14 16 Memory (Data) 8 Memory (Program) CPU Memory (Program &Data)
  • 7. Why do we need DSP Processor?
  • 9.
  • 10.
  • 11.
  • 13.
  • 14.
  • 16.
  • 17. Traditional embedded system design using DSP Power Supply CLK CLK CLK custom IF-logic SDRAM SDRAM SRAM SRAM SRAM Memory Controller UART LC Display Controller Interrupt Controller Timer Audio Codec CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC
  • 18. Next Step... CLK custom IF-logic Memory Controller UART Display Controller Timer CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC Interrupt Controller FPGA CLK CLK SDRAM SDRAM SRAM SRAM SRAM Power Supply LC Audio Codec
  • 19. Configurable system on Chip-CSoC Power Supply SDRAM SDRAM SRAM SRAM SRAM LC Audio Codec EPROM
  • 20.
  • 21. SMP-BF561 • Identical Cores • Identical access to all System Resources • Memory, Disk, UARTs, Communication Controllers, • Examples: Analog Devices Blackfin 561
  • 22.
  • 23.
  • 24. Selection of packages QFP SOLDERING IRON SOLDERING STATION OVEN DIP SOIC BGA PLCC
  • 25. Hardware Design Flow SCHEMATIC DESIGN LAYOUT DESIGN ASSEMBLY & TESTING
  • 26.
  • 28. Software Design Flow -FPGA Generate Netlist ISE Platform Ext. Proj.Nav. / VHDL *.mhs *. elf *.c *.asm Compile & Link Update Bitstream *. bit *.h Gen. Libs Platform Definition (peripherals, configuration, connectivity, address space)  EDK: Embedded Development Kit  XPS: Xilinx Platform Studio  ISE: Integrated Software Environment  MHS: Microprocessor Hardware Specification *. bit XPS Generate Bitstream *.ucf Hardware Software *.bmm
  • 29. RTOS, Board Support Package Integrated HW/SW/FPGA Flows Instantiate the ‘ System Netlist’ and Implement the FPGA Include the BSP and Compile the Software Image 1 2 3 Xilinx Platform Studio SDK Xilinx Platform Studio Data2MEM Download Combined Image to FPGA Compiled ELF Compiled BIT Embedded Development Kit ? HDL Entry Simulation/Synthesis Implementation Download Bitstream Into FPGA Chipscope Standard FPGA HW Development Flow VHDL or Verilog System Netlist ? Code Entry C/C++ Cross Compiler Linker Load Software Into FLASH Debugger Standard Embedded SW Development Flow C Code Board Support Package Compiled BIT Compiled ELF
  • 30. FPGA Design Flow
  • 31. Design Compilation Simulation Verification Graphical Entry HDL Entry Compiler Timing Diagram Timing Analysis Program CPLD Development Board FPGA Design Flow
  • 32. Unified Tool Releases, All Tools Available for Evaluations Verilog VHDL C/C++ MATLAB Simulink 3 rd Party Unified Design Environment The Ultimate System Integration Design Tools New ! HW Designers SW Developers Architects Verification Team System Integrators . . . .
  • 33. Design Decision in Choosing an FPGA Programmable technology Gate count Number of I/O’S Manufacturer Family Device Power Consumption Speed,voltage Packaging
  • 34.
  • 35. SW DEVELOPMENT HW DEVELOPMENT SW SELECTION HW SELECTION INTEGRATION TESTING & TUNING DEPLOYMENT Compiler RTOSs Networking Protocols Java Support Graphics Support Project & Code Mgmt. RTOS Simulation Rapid Prototyping Real-time Data Visualization Memory Leak Detection CPU Profiling Post-mortem Debug Semiconductor Co-funded Development Hardware Coverage Board Bring-Up Board Diagnostics & Manufacturing Test Source-level Debugging Real-time System Analysis & Triggering Execution Tracing Code Coverage Analysis In-field Debugging © 2008 Pantech Solutions™ | All rights reserved Embedded Development using FPGA
  • 36.
  • 38.
  • 39. Recap of Designing an Embedded System
  • 41. http://www.esacademy.com/ 8051 (Philips Flash ISP software) http://www.keil.com/demo/ Evaluation version for 8051 and ARM http://www.microchip.com PIC FPGA http://www.xilinx.com/support/download/index.htm https://www.altera.com/support/software/download/sof-download_center.html http://www.analog.com/en/embedded-processing-dsp/content/blackfin_bold_training/fca.html DSP www.ti.com/
  • 43.