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Registers & Counters
Course: B.Sc.(CS)
Subject: Basics of Digital Electronics
Unit : 3rd
Sem.:1st
COUNTERS
 Why do we need counters?
 Counters in digital circuits may used for 3 functions:
 Timing: Building a precision digital clock is an
example where a low frequency (10 Hz) clock
cannot be achieved with a crystal oscillator.
 Sequencing: Starting of a rocket motor is an
example where the energizing of fuel pumps,
ignition, etc. must follow a critical sequence.
 Counting: Measuring the flow of traffic on a road
is an application in which the total number of
vehicles passing a certain point needs be counted.
COUNTERS (continued)
 A counter is a register that goes through a sequence
of states.
 Counter categories:
 1. Ripple counters
 2. Synchronous counters
 • Ripple counters: The flip- flop’s output transition
triggers other flip- flops.
 • Synchronous counters: A common clock triggers
all flip- flops simultaneously rather than one at a time
in succession as in ripple counters.
BINARY RIPPLE COUNTER
 A binary ripple counter consists of a series
connection of complementing flip-flops à the output
of each flip-flop is connected to the C input of the
next higher-order flip-flop.
BINARY RIPPLE COUNTER
BINARY RIPPLE COUNTER
 Q0 is complemented with the count pulse. Since Q1
goes from 1 to 0, it triggers Q1 and complements it.
As a result, Q1 goes from 1 0, which in turn
complements Q2 changing it from 0 1. Q2 does not
trigger Q3 because Q2 produces a positive transition.
The flip-flops change one bit at a time in succession
and the signal propagates through the counter in a
ripple fashion from one stage to the next.
BINARY RIPPLE COUNTER
PROBLEMS WITH RIPPLE COUNTERS
 Asynchronous or ripple counters are arranged in
such a way that the output of one flip flop changes
the state of the next. In a long chain of ripple counter
stages, the last flip flop changes its state
considerably later than the first FF due to
propagation delays in each stage. Problems occur if
this delay is longer than the response time of other
logic elements connected to the circuit.
 Synchronous counters overcome the problems
of propagation delay and erroneous intermediate
states. In this type of counter all the FF clock inputs
are wired together, so the transitions of all stages
occur simultaneously.
SYNCHRONOUS COUNTERS
 Synchronous counters are different from ripple counters
in that the clock is applied to the inputs of all flip-flops,
which triggers all flip flops at the same time.
 If T = 0 or J = K = 0, the flip- flop does not change state.
 If T = 1 or J = K = 1, the flip- flop complements.
 Suppose for a 4-bit counter A3A2A1A0= 0011, the next
count is 0100.
 A0is always complemented.
 A1is complemented because the present state of A0 =1.
 A2 is complemented because the present state of A1A0
=11.
 A3 is not complemented because the present state of
A2A1A0 =011.
4-BIT SYNCHRONOUS COUNTER
 If the enable is 0 and, all J and K inputs are 0
and the clock does not change the state of
counter.
 The first stage A has its J and K = 1 if enable = 1.
 The other J and K are equal to 1 if all previous 0
least significant stages are equal to 1. The chain
of AND gates generates the required logic for the
J and K inputs in each stage.
 Note that Synchronous counters have a regular
pattern.
4-BIT SYNCHRONOUS COUNTER
Registers & Counters
 A register consists of a group of flip- flops and gates
that affect their transition. An n-bit register consists
of n-bit flip-flops capable of storing n bits of binary
information.
 In addition to flip- flops, a register may have
combinational gates that perform certain data
processing tasks.
 A counter is essentially a register that goes through
a pre-determined sequence of states. The gates in
the counter are connected in such a way to produce
the prescribed sequence of states.
BINARY RIPPLE COUNTER
 A binary ripple counter consists of a series
connection of complementing flip-flops à the
output of each flip-flop is connected to the C
input of the next higher-order flip-flop.
4-Bit Register
 The common clock input triggers all flip- flops on
the positive edge of each pulse à the binary data
available at the 4 inputs are transferred into the
register.
 The four outputs can be sampled to obtain the
binary information stored in the register.
 When the clear input R goes to zero, all flip- flops
are reset (register is cleared to 0’s)
Fig. 4 Bit Register
Register with Parallel Load
 When load input = 1 à data transferred into
register with next clock edge.
 When load input = 0 à outputs of Flip-Flops are
connected to their inputs.
Fig: 4 Bit register with parallel load
Shift Registers
 A Shift Register is a register that is capable of
shifting its binary information in one or both
directions.
 On the leading edge of the first clock pulse, the
signal on the data in is latched in the first flip-
flop. On the leading edge of the next clock pulse,
the contents of the first flip- flop is stored in the
second flip- flop, and the signal which is present
at the data in is stored is the first flip- flop, etc.
Serial Shift Registers – Timing Diagram
Serial Transfer
prevents
loss
of
information
determines when
and how many
times the registers
are shifted.
Each rising edge
of pulse causes a
shift in both
registers
Serial Transfer Example 1
Serial Transfer Example 1 (continued)
 With the first pulse T1, (a) the rightmost bit of A is
shifted into the leftmost bit of B and (b) also
circulated into the leftmost position of A.
 At the same time, (c) all bits of A and B are shifted
one position to the right.
Serial/Parallel Computation
 Communication between a computer and a
peripheral device is usually done serially, while
computation in the computer itself is usually
performed with parallel logic circuitry.
 Computations in the computer are done in
parallel because this is a faster mode. Serial
operations are slower but require less devices.
Fig: 4 Bit Adder with Carry Look ahead & 4
Bit Adder- Subtractor.
Serial Addition
 Initially, Reg. A holds the augend (# to which another
# is added), B holds the addend (the # that is
added). Shift control enables both Reg.’s, and carry
FlipFlop, so that at the next, both Reg.’s are shifted
once to the right, the sum bit from S enters the
leftmost Flip-Flop of A, a new carry is transferred to
Q, and both registers are shifted once to the right.
Thus, the sumis transferred one at a time into Reg.
A.
Fig: Serial Adder
Parallel Adder vs. Serial Adder
Parallel Adder vs. Serial Adder
 1. Parallel adder uses parallel loading, whereas
the serial adder uses shift registers.
 2. Number of full adder circuit in the parallel
adder is equal to the number of bits in the binary
numbers. Serial adder requires only one full
adder and a carry Flip -Flop.
 3. The parallel adder is a combinational circuit,
whereas the serial adder is a sequential circuit
that consists of a full adder and a Flip-Flop.
Universal Shift Register
 A universal shift register is a bidirectional shift
register with parallel load capabilities.
Universal Shift Register
Universal Shift Register
 • When S1S0 = 11, the binary information on the
parallel input lines is transferred into the register
simultaneously at the next clock edge.
 • When S1S0= 00, the present value of the register
is applied to the D inputs of the FFs. This forms a
conduction path from the output to the input of each
FF.
 • When S1S0= 01, terminal 1 of the multiplexer
inputs has a path to the D inputs of the FFs, which
causes a shift-right operation, with serial input
transferred into FF A3.
 • When S1S0= 10, a shift-left operation results
with serial input going into FF A0.
Universal Shift Register
Parallel vs. Serial Data Transmission
 Shift registers are often used to interface digital
systems situated remotely from each other.
 Task: We want to transmit an n-bit quantity between
two location that are far from each other.
 What are the options?
 1. Use n lines to transmit n bits in parallel. Problem:
Cost is expensive.
 2. Use a single line to transmit the information
serially, one bit at a time.
 Cost is less.
References
 Digital Logic and Computer Design – M. Morris Mano
– Pearson
 Fundamentals of Digital Circuits – A. Anand Kumar -
PHI
 Digital Electronics - Gothmen - PHI
 Digital Electronics Principles - Malvino & Leech -
MGH
 Digital fundamentals - Thomes L.Floyd and Jain -
Pearson
 Modern Digital Electronics - R.P. Jain - TMH
Web References
 media.careerlauncher.com.s3.amazonaws.com/gate/
material/2.pdf
 http://www.faadooengineers.com/threads/346-
Digital-Electronics-Lecture-notes-and-study-material
 http://media.careerlauncher.com.s3.amazonaws.com
/gate/material/2.pdf
 Image References:
 http://www.youshouldgoaway.com/wp-
content/uploads/2014/11/thankyou.jpg
B sc cs i bo-de u-iii counters & registers

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B sc cs i bo-de u-iii counters & registers

  • 1. Registers & Counters Course: B.Sc.(CS) Subject: Basics of Digital Electronics Unit : 3rd Sem.:1st
  • 2. COUNTERS  Why do we need counters?  Counters in digital circuits may used for 3 functions:  Timing: Building a precision digital clock is an example where a low frequency (10 Hz) clock cannot be achieved with a crystal oscillator.  Sequencing: Starting of a rocket motor is an example where the energizing of fuel pumps, ignition, etc. must follow a critical sequence.  Counting: Measuring the flow of traffic on a road is an application in which the total number of vehicles passing a certain point needs be counted.
  • 3. COUNTERS (continued)  A counter is a register that goes through a sequence of states.  Counter categories:  1. Ripple counters  2. Synchronous counters  • Ripple counters: The flip- flop’s output transition triggers other flip- flops.  • Synchronous counters: A common clock triggers all flip- flops simultaneously rather than one at a time in succession as in ripple counters.
  • 5.  A binary ripple counter consists of a series connection of complementing flip-flops à the output of each flip-flop is connected to the C input of the next higher-order flip-flop. BINARY RIPPLE COUNTER
  • 7.  Q0 is complemented with the count pulse. Since Q1 goes from 1 to 0, it triggers Q1 and complements it. As a result, Q1 goes from 1 0, which in turn complements Q2 changing it from 0 1. Q2 does not trigger Q3 because Q2 produces a positive transition. The flip-flops change one bit at a time in succession and the signal propagates through the counter in a ripple fashion from one stage to the next. BINARY RIPPLE COUNTER
  • 8. PROBLEMS WITH RIPPLE COUNTERS  Asynchronous or ripple counters are arranged in such a way that the output of one flip flop changes the state of the next. In a long chain of ripple counter stages, the last flip flop changes its state considerably later than the first FF due to propagation delays in each stage. Problems occur if this delay is longer than the response time of other logic elements connected to the circuit.  Synchronous counters overcome the problems of propagation delay and erroneous intermediate states. In this type of counter all the FF clock inputs are wired together, so the transitions of all stages occur simultaneously.
  • 9. SYNCHRONOUS COUNTERS  Synchronous counters are different from ripple counters in that the clock is applied to the inputs of all flip-flops, which triggers all flip flops at the same time.  If T = 0 or J = K = 0, the flip- flop does not change state.  If T = 1 or J = K = 1, the flip- flop complements.  Suppose for a 4-bit counter A3A2A1A0= 0011, the next count is 0100.  A0is always complemented.  A1is complemented because the present state of A0 =1.  A2 is complemented because the present state of A1A0 =11.  A3 is not complemented because the present state of A2A1A0 =011.
  • 11.  If the enable is 0 and, all J and K inputs are 0 and the clock does not change the state of counter.  The first stage A has its J and K = 1 if enable = 1.  The other J and K are equal to 1 if all previous 0 least significant stages are equal to 1. The chain of AND gates generates the required logic for the J and K inputs in each stage.  Note that Synchronous counters have a regular pattern. 4-BIT SYNCHRONOUS COUNTER
  • 12. Registers & Counters  A register consists of a group of flip- flops and gates that affect their transition. An n-bit register consists of n-bit flip-flops capable of storing n bits of binary information.  In addition to flip- flops, a register may have combinational gates that perform certain data processing tasks.  A counter is essentially a register that goes through a pre-determined sequence of states. The gates in the counter are connected in such a way to produce the prescribed sequence of states.
  • 13. BINARY RIPPLE COUNTER  A binary ripple counter consists of a series connection of complementing flip-flops à the output of each flip-flop is connected to the C input of the next higher-order flip-flop.
  • 14.
  • 15. 4-Bit Register  The common clock input triggers all flip- flops on the positive edge of each pulse à the binary data available at the 4 inputs are transferred into the register.  The four outputs can be sampled to obtain the binary information stored in the register.  When the clear input R goes to zero, all flip- flops are reset (register is cleared to 0’s)
  • 16. Fig. 4 Bit Register
  • 17. Register with Parallel Load  When load input = 1 à data transferred into register with next clock edge.  When load input = 0 à outputs of Flip-Flops are connected to their inputs.
  • 18. Fig: 4 Bit register with parallel load
  • 19. Shift Registers  A Shift Register is a register that is capable of shifting its binary information in one or both directions.  On the leading edge of the first clock pulse, the signal on the data in is latched in the first flip- flop. On the leading edge of the next clock pulse, the contents of the first flip- flop is stored in the second flip- flop, and the signal which is present at the data in is stored is the first flip- flop, etc.
  • 20. Serial Shift Registers – Timing Diagram
  • 21. Serial Transfer prevents loss of information determines when and how many times the registers are shifted. Each rising edge of pulse causes a shift in both registers
  • 23. Serial Transfer Example 1 (continued)  With the first pulse T1, (a) the rightmost bit of A is shifted into the leftmost bit of B and (b) also circulated into the leftmost position of A.  At the same time, (c) all bits of A and B are shifted one position to the right.
  • 24. Serial/Parallel Computation  Communication between a computer and a peripheral device is usually done serially, while computation in the computer itself is usually performed with parallel logic circuitry.  Computations in the computer are done in parallel because this is a faster mode. Serial operations are slower but require less devices.
  • 25. Fig: 4 Bit Adder with Carry Look ahead & 4 Bit Adder- Subtractor.
  • 26. Serial Addition  Initially, Reg. A holds the augend (# to which another # is added), B holds the addend (the # that is added). Shift control enables both Reg.’s, and carry FlipFlop, so that at the next, both Reg.’s are shifted once to the right, the sum bit from S enters the leftmost Flip-Flop of A, a new carry is transferred to Q, and both registers are shifted once to the right. Thus, the sumis transferred one at a time into Reg. A.
  • 28. Parallel Adder vs. Serial Adder
  • 29. Parallel Adder vs. Serial Adder  1. Parallel adder uses parallel loading, whereas the serial adder uses shift registers.  2. Number of full adder circuit in the parallel adder is equal to the number of bits in the binary numbers. Serial adder requires only one full adder and a carry Flip -Flop.  3. The parallel adder is a combinational circuit, whereas the serial adder is a sequential circuit that consists of a full adder and a Flip-Flop.
  • 30. Universal Shift Register  A universal shift register is a bidirectional shift register with parallel load capabilities.
  • 32. Universal Shift Register  • When S1S0 = 11, the binary information on the parallel input lines is transferred into the register simultaneously at the next clock edge.  • When S1S0= 00, the present value of the register is applied to the D inputs of the FFs. This forms a conduction path from the output to the input of each FF.  • When S1S0= 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the FFs, which causes a shift-right operation, with serial input transferred into FF A3.  • When S1S0= 10, a shift-left operation results with serial input going into FF A0.
  • 34. Parallel vs. Serial Data Transmission  Shift registers are often used to interface digital systems situated remotely from each other.  Task: We want to transmit an n-bit quantity between two location that are far from each other.  What are the options?  1. Use n lines to transmit n bits in parallel. Problem: Cost is expensive.  2. Use a single line to transmit the information serially, one bit at a time.  Cost is less.
  • 35. References  Digital Logic and Computer Design – M. Morris Mano – Pearson  Fundamentals of Digital Circuits – A. Anand Kumar - PHI  Digital Electronics - Gothmen - PHI  Digital Electronics Principles - Malvino & Leech - MGH  Digital fundamentals - Thomes L.Floyd and Jain - Pearson  Modern Digital Electronics - R.P. Jain - TMH
  • 36. Web References  media.careerlauncher.com.s3.amazonaws.com/gate/ material/2.pdf  http://www.faadooengineers.com/threads/346- Digital-Electronics-Lecture-notes-and-study-material  http://media.careerlauncher.com.s3.amazonaws.com /gate/material/2.pdf  Image References:  http://www.youshouldgoaway.com/wp- content/uploads/2014/11/thankyou.jpg