* Why need to use High Frequency low power Device?? * Introduction * Design Developments * Chipset Design * Transmitter Chip * Receiver Chip * Measurement * Result of Power Consumption * Conclusion

1. 98 mW 10 Gbps Wireless Transceiver
Chipset With D-Band CMOS Circuits
Authors
Minoru Fujishima, Mizuki Motoyoshi, Kosuke
Katayama, Kyoya Takano, Naoko Ono and Ryuichi
Fujimoto
Reference
IEEE Journal of Solid State Circuits Volume 48 No. 10
October, 2013
Presented By
Md. Saifur Rahman
Roll: 0903027

2. Outlines
* Why need to use High Frequency low power Device??
* Introduction
* Design Developments
* Chipset Design
* Transmitter Chip
* Receiver Chip
* Measurement
* Result of Power Consumption
* Conclusion

3. Why need to use High Frequency
low power Device??
Figure 1: Evaluation of data rates
in wired and wireless
communication
Figure 2: Evaluation of maximum
operational frequency fmax

4. Introduction
• D-Band (110-170 GHz)
• Current operation is 60 GHz
• 100 Gbps operation will appear
around 2020.
• Not possible to enlarge the adaptor
size for handling large power.
• Have to design low power device.
Figure 3: Chip development process in
the cases of (a) general analog RF
circuits (b) millimeter wave circuits

5. Design Developments
Figure 5: Chip micrograph after
probing of on-chip devices
Figure 4: Complex layout diagram of CMOS circuit

6. Figure 6: (a) Basic RF design model (b)
comparison of reflection characteristics
of transmission parameters S11 & S22
Figure 7: Measured of NQS
Delay of a MOSFET

7. Figure 8: (a) Wrapper admittance
matrix Ywrap (b) equivalent circuit
Figure 9: Comparison of
transmission parameters S11 &
S22 of wrapped model

8. Figure 10: One stage common
source amplifier of wrapped
model
Figure 11: Comparison of measured and wrapped model

9. Figure 12: Comparison of frequency and
time domain response

10. Chipset Design
Figure 13: Chip micrograph of 135 GHz COMS amplifier fabricated with
65 nm CMOS process. It has five stages common source amplifiers

11. Figure 14: Block diagram of 135
GHz CMOS transceiver chipset
Figure 15: Target operation
frequency for D-Band CMOS
transceiver

12. Transmitter Chip
Figure 16: Block diagram of
(a)conventional ASK transmitter
(b) proposed power amplifier free
ASK transmitter
Figure 17: Simulated power
output and power
consumption as a function of
load impedance

13. Figure 18: (a) Power contour
plot (b) schematic of 135 GHz
COMS transceiver
Figure 19: (a)
Simulation result
of insertion loss
(b) Trajectories of
load impedance

14. Figure 20: Output power and power consumption
Figure 21: (a) Output spectrum of
transmitter (b)modulated output
spectrum

15. Receiver Chip
Figure 22: Co Design of D-Band
amplifier with detector (b)
Frequency response block diagram of
gain and group delay
Figure 23: Simulated
frequency response of gain
and group delay

16. Measurement of Chip
Figure 24: Chip micrograph of Tx and Rx
Figure 25: Measurement setup of the transmitter and receiver
with wireless signal

17. Result of Power Consumption
Here is the measured
power consumption of
the transmitter and
receiver. The power
consumption is 17.9 mW
for the transmitter and
80.5 mW for the receiver.
The total power
consumption is 98.4 mW
Figure 26: Measure power
consumption of the transmitter
and receiver

18. Conclusion
* Development of CMOS Chip for D-Band
Transceiver
* 135 GHz 98 mW 10 Gbps ASK Transmitter and
Receiver.
* The chipset is fabricated in 40 nm technology.
* A power amplifier free architecture is adopted
to realize low power operation
* The chipset is verified with wireless
propagation test with 10 cm distance over 100
GHz.

19. Thank you