1. Real-time Analysis and Simulation of Multi-string
Grid-connected Photovoltaic inverter using FPGA
Presented by-
Satabdy Jena
MTech (Power & Energy Systems)
Department of Electrical Engineering
NIT Meghalaya
Satabdy Jena, Gayadhar Panda and Rangababu Peesapati
2. Contents
1. Introduction
2. Proposed System Structure
3. Control Algorithm
4. Field Programmable Gate Array
5. Xilinx System Generator
6. Hardware Co-Simulation
7. Conclusion
8. References
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3. 1.Introduction
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Dearth of energy, trend of rising prices and limited resources.
Abundant availability of solar energy has lead to installation of large-scale Photovoltaic
systems(standalone or grid-connected).
• Grid synchronization
• Grid disturbances
Frequency
Voltage
• Industry design standards
4. 2.Proposed System Structure
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PV2
MPPT1
MPPT2
PWM1
PWM2
SPWM PLL
Modulating
Signal
Generation
CURRENT
CONTROLLER
VOLTAGE
CONTROLLER
PV1
+-
V*dc
Vdc
3-ф
3-Level
Central
Inverter
Filter
Inductance
Isolation
Transformer
ia,b,c ua,b,c
iq*
id* idq
udq
Utilty grid
abc
dq
ud* uq*
DC/DC
Boost Converter1
DC/DC
Boost Converter2
LfRf
Cf LtRt
ϴ
ϴ
Reference
Signal
Generation
mdq
FPGA Based Control Circuit
MULTI-STRING PV ARRAY
ipv1
ipv2
vpv1
vpv2
LOAD
Fig.1. Structure of proposed system
5. Terminology Description Terminology Description
Vpv, Ipv PV voltage and current Lt, Rt Transformer inductance and
resistance
Vdc Capacitor voltage Ls, RS Equivalent inductance and
resistance
ua, ub, uc Grid line voltages Lt, Rt Transformer inductance and
resistance
ia, ib, ic Grid line currents id, iq d and q-axes currents
Lf, Rf Filter inductance and
resistance
ud, uq d and q-axes voltages
Lg, Rg Grid inductance and
resistance
mdq Modulating signals
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Table 1. System Terminology description
6. 3.Control Algorithm
(a) MPP Tracking
• Incremental Conductance (Inc)
-by comparing instantaneous (
Ipv
Vpv
) and incremental conductance (
dIpv
dVpv
), the MPP voltage of the PV
array is obtained.
dPpv
dVpv
=
d(VpvIpv)
dVpv
= 0 =>
Ipv
Vpv
+
dIpv
dVpv
= 0. (1)
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Fig.2. P-V characteristics of PV array
7. (b) Inner and Outer Control loop design for VSI
-Decoupling Technique
• ud
∗
= Kpd id
∗
− id + Kid (id
∗
− id)dt − ωL 𝑠 𝑖 𝑞 + ud (2)
• uq
∗ = Kpq iq
∗ − iq + Kiq (iq
∗ − iq)dt + ωL 𝑠 𝑖 𝑑 + uq
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Switching
State
Switch
configuration
Voltage
+1 1100 Van
0 0110 0
-1 0011 -Van
Fig.3. Outer and Inner Loop Design
Fig.4. Three-level Inverter Structure
Table 2. Switching states for the inverter
8. (c) Grid Synchronization
-Phase Locked Loop
A feedback system with a PI regulator tracking the phase angle .
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𝐺 𝑜𝑙 = (𝐾 𝑃
1+𝑠𝜏
𝑠𝜏
)(
1
1+𝑠𝜏
)(
𝑉𝑚
𝑠
) (3)
-100
-50
0
50
100
Magnitude(dB)
System: sys1
Frequency (rad/s): 314
Magnitude (dB): 0.0119
10
0
10
1
10
2
10
3
10
4
10
5
-180
-150
-120
-90
System: sys1
Frequency (rad/s): 314
Phase (deg): -108
Phase(deg)
Bode Diagram
Frequency (rad/s)
-100
-50
0
50
Magnitude(dB)
10
1
10
2
10
3
10
4
10
5
-180
-135
-90
-45
0
Phase(deg)
Bode Diagram
Frequency (rad/s)
Fig.5. Block diagram of PLL
Fig.6. Bode plot for Open loop system Fig.7. Bode plot for closed loop system
9. 4.Field Programmable Gate Array
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An FPGA is a programmable breadboard for digital circuits-on-chip.
It consists of:
Programmable Logic Elements
Programmable Interconnects
Custom Circuitry
Fig.8.FPGA Configuration
11. 5.Xilinx System Generator
A DSP-design tool.
Provides users with Xilinx block-set in Matlab/Simulink.
Automatic synthesis and place-and-route.
Bit-accurate and Cycle-accurate.
Handle VHDL, C or m-code.
Handle multiple sampling rates.
Generates a run-time hardware block (JTAG).
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12. • Precision and sampling time.
• Fixed and Floating-point representation.
• Clock period=40 ns.
• 75 MHz.
• Compatibility between different data-point types.
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6.Implementation in FPGA
13. Implementation in FPGA (contd.)
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Fig.10. Voltage controller in Xilinx blockset
Fig.11. SPWM in Xilinx blockset
Fig.12. Current controller in Xilinx blockset
Fig.13. PLL in Xilinx blockset
16. 7.Hardware Co-Simulation
System parameters Value System parameters Value
Series connected modules 7(PV1) (PV2) DC Link voltage 750 V
Parallel connected modules 20(PV1) 30 (PV2) Filter inductance and resistance 1 mH, 3 mΩ
MPP Voltage 54.7 V Grid inductance and resistance 16 mH, 0.8929 Ω
MPP Current 5.58 A Transformer inductance and resistance 0.06 mH, 0.002 mΩ
Open-circuit voltage 64.2 V Inverter switching frequency 5 .5 kHz
Short-circuit current 5.96 A Boost switching frequency 5 kHz
Maximum PV power 85.5 kW Grid voltage 22 kV
DC Link capacitor 5000 μF Grid frequency 50 Hz
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Table 2. System Parameters
A test system consisting of a multi-string PV array connected to a 400 V three phase source via
a multilevel inverter has been considered. A local load consuming 10 kW of active power is
connected at the PCC.
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Fig.16. Irradiation Fig.17. Power consumed by load and grid
Fig.18. Power generation by the multi-string PV array
Case 1: Varying irradiance condition
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0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
-200
-150
-100
-50
0
50
100
150
200
X= 1.1846
Y= 77.2305
Time (sec)
i_a(A)
X= 0.80466
Y= 187.9812
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
-400
-300
-200
-100
0
100
200
300
400
i_a/u_a(A/V)
Time (sec)
ia
ua
Fig.19. Grid injected current
Fig.20. Grid voltage and current
Fig.21. Frequency
Fig.22. THD of grid injected currents
19. Case 2: Dynamic loading condition
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Fig.23. Grid injected current Fig.24. Load current
Fig.25. Real power exchange
P=10 kW, 1 kVAr to at t=0.8-1.5 s,P=100 kW, Q=15 kVAr
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Fig.28. Simulation and hardware results of SPWM Fig.29. Simulation and hardware results of PLL
Fig.30. Simulation and hardware results of d-axis current Fig.31. Simulation and hardware results of q-axis current
Fig.32. Simulation and hardware results of reference signal
23. 7.Conclusion
The proposed system was thus implemented in Matlab/Simulink and its real-time performance was
validated using FPGA. The performance of the system was analyzed and the correlation with the
theoretical evaluation was established. It is observed that the critical path delay is 9.5 ns.
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24. 8.References
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[11] Kaura and V. Blasko,“Operation of a Phase Locked Loop System Under Distorted Utility Conditions,” Eleventh Annual Proceedings of
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[13] Dean Banerjee,“PLL Performance, Simulation and Design,” 4th Edition,Dog Ear Publishing
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