This is a ppt by Sir Sanjoy Banerjee, my microprocessor and microcontroller teacher. Plz Visit: www.karaoke-cosmos.blogspot.com

1. A N I NTRODUCTION T O 8051 M ICROCONTROLLER A ND I TS A PPLICATION Presented by S ANJOY B ANERJEE LECTURER

3. It is a programmable computer but not itself a general purpose system. It is a hardware platform with Microprocessor and I/O devices which support required tasks and implement software that perform the required processing. EMBEDDED SYSTEM

7. CPU Read/Write RAM ROM Printer Keyboard Monitor Disk DATA BUS CONTROL BUS ADDRESS BUS Internal Organisation Of Computers

9. (a) General- Purpose Microprocessor System (b) Microcontroller CPU General- Purpose Microproc- essor RAM ROM I/O PORT Timer Serial COM Port CPU RAM ROM I/O Timer Serial COM Port

22. Choice of Processors Processors Microcontroller Microprocessor DSP 8 bit : 8085 Z80 6800 16 bit : 8086 Z8000 68000 32 bit : Pentium PowerPC 68000 8 bit : 8051 & derivatives Microchip PIC series 16 bit : Intel 80196 Microchip PIC series Texas MSP series 32 bit : ARM based Microcontrollers PowerPC based microcontrollers 16/32 bit : Blackfin ADSP-BF53x SHARC ADSP-21xxx Texas TMS320 series

23. ARM-7 based µC from NXP

24. 16 bit MCU from Texas Architecture of MSP430F2013

26. MCUs Architecture Memory (program +data) CPU Memory (program) Memory (data) CPU Von Neumann Harvard ADDRESS DATA ADDRESS ADDRESS DATA DATA

29. Arithmetic And Logic Unit PSW A B Special Function Register RAM PC DPTR DPH DPL ROM Port 0 Latch Port 1 Latch Port 2 System Timing System Interrupts Timer Data Buffers Memory Controls Latch Port 3 Latch Register Bank 0 Register Bank 1 Register Bank 2 Register Bank 3 Byte/Bit Address TLO THO TL1 TH1 TMOD TCON Special Function Register PCON SCON SBUF IP IE EA ALE PSEN XTAL 1 XTAL 2 RESET VCC GND 16-Bit Address Bus I/O A0-A7 D0-D7 I/O I/O A8-A15 I/O Interrupt Counter Serial Data RD-WR Internal RAM Structure 8051 family micro controller

30. 8051 ARCHITECTURE

31. Features of the 8051 6 Interrupt sources 1 Serial port 32 I/O pins 2 Timer 128 bytes RAM 4K bytes ROM Quantity Feature

32. Comparison of 8051 Family Members 6 8 6 Interrupt sources 1 1 1 Serial port 32 32 32 I/O pins 2 3 2 Timers 128 256 128 RAM 0K 8K 4K ROM(on-chip program space in bytes) 8031 8052 8051 Feature Various 8051 Micro controllers

34. 8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIN DESCRIPTION

39. Oscillator and Clock contd .

40. Reset Circuit

43. P0 PORT contd.

52. FLAGS Contd. Select register bank 3 1 1 Select register bank 2 0 1 Select register bank 1 1 0 Select register bank 0 0 0 REGISTER RS1 RS0

54. Problem1: Show the status of the CY, AC, and P flags after the addition of 38H and 2FH in the following instructions. MOV A, #38H ADD A, #2FH Problem2: Show the status of the CY, AC, and P flags after the addition of 9CH and 64H in the following instructions. MOV A, #9CH ADDC A, #64H

56. INTERNAL RAM Contd.

57. INTERNAL RAM Contd.

58. INTERNAL RAM Contd. BANK 0 BANK 1 BANK 2 BANK 3 WORKING REGISTER R0 0 R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 NAME ADD NAME ADD R0 18 R1 19 R2 1A R3 1B R4 1C R5 1D R6 1E R7 1F NAME ADD R0 8 R1 9 R2 A R3 B R4 C R5 D R6 E R7 F NAME ADD R0 10 R1 11 R2 12 R3 13 R4 14 R5 15 R6 16 R7 17

59. INTERNAL RAM Contd. 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 BYTE ADD BIT ADDRESS B I T A D D R E S S A B L E R E G I S T E R BYTE ADD GENERAL PURPOSE 30 7F 07 06 05 04 03 02 01 00 0F 0E 0D 0C 0B 0A 09 08 17 16 15 14 13 12 11 10 1F 1E 1D 1C 1B 1A 19 18 27 26 25 24 23 22 21 20 2F 2E 2D 2C 2B 2A 29 28 37 36 35 34 33 32 31 30 3F 3E 3D 3C 3B 3A 39 38 47 46 45 44 43 42 41 40 4F 4E 4D 4C 4B 4A 49 48 57 56 55 54 53 52 51 50 5F 5E 5D 5C 5B 5A 59 58 67 66 65 64 63 62 61 60 6F 6E 6D 6C 6B 6A 69 68 77 76 75 74 73 72 71 70 7F 7E 7D 7C 7B 7A 79 78

61. PSW Bits Bank Selection Example: State the contents of the RAM locations after the following program: SETB PSW.4 ; select bank 2 MOV R0,#99H ; load R0 with value 99H MOV R1,#85H ; load R1 with value 85H MOV R2,#3FH ; load R2 with value 3FH MOV R7,#63H ; load R7 with value 63H MOV R5,#12H ; load R5 with value 12H Solution: By default, PSW.3=0 and PSW.4; therefore, the instruction “SETB PSW.4” sets RS1=1 and RS0=0, thereby selecting register bank 2. Register bank 2 uses RAM location 10H-17H. After the execution of the above program we have the following: RAM location 10H has value 99H RAM location 11H has value 85H RAM location 12H has value 3FH RAM location 17H has value 63H RAM location 15H has value 12H 1 1 Bank 3 0 1 Bank 2 1 0 Bank 1 0 0 Bank 0 RS0 (PSW.3) RS1 (PSW.4)

65. SPECIAL FUNCTION REGISTER Contd .. 8D Timer 1 High byte TH1 8B Timer 1 low byte TL1 8C Timer 0 high byte TH0 8A Timer 0 low byte TL0 88 Timer/ Counter control TCON 89 Timer/ Counter mode control TMOD 81 Stack pointer SP 99 Serial port data buffer SBUF 98 Serial port control SCON 0D0 Program status word PSW 87 Power control PCON 0B0 Input/output port latch P3 0A0 Input/output port latch P2 90 Input/output port latch P1 80 Input/output port latch P0 0B8 Interrupt priority IP 0A8 Interrupt enable control IE 82 Addressing external moeory DPL 83 Addressing external moeory DPH 0F0 Arithemetic B 0E0 Accumulator A Internal RAM Address (Hex) Function Name

68. A MICROCONTROLLER DESIGN

71. RD WR EA P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 2864 (2764) 8K*8 PROGRAM ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8031 A0 Vcc A12 A8 D7 D0 Connection to External program ROM G CONNECTION WITH EXTERNAL PROGRAM ROM

72. OFF CHIP ON-CHIP OFF CHIP ON-CHIP OFF CHIP 8031/51 EA=GND 0000 FFFF 8051 EA=Vcc 8052 EA=Vcc 0000 0FFF 1000 FFFF 0000 1FFF 2000 FFFF On chip and off-chip program code Access On chip-off chip ROM

73. RD WR P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 8K*8 DATA ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8051 A0 Vcc A12 A8 D7 D0 8051 Connection to External Data ROM A15 A14 A13 G Connection with external data ROM

74. EA PSEN P3.7 P3.6 P2.7 P0.0 P0.7 ALE P2.0 8051 8031 Connection to External Data ROM and External program ROM RD WR AD0 8K*8 DATA ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 A0 Vcc A12 A8 D7 D0 A15 A14 A13 G 2864 (2764) 8K*8 PROGRAM ROM Vpp OE CE A12 A8 A7 A0 D0 D0 Vcc D7 Connection to External Data ROM and External program ROM

75. RD WR P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 8K*8 DATA RAM OE WE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8051 A0 A12 A8 D7 D0 8051 Connection to External data RAM G A14 A13 A15 A13 Connection with external data RAM

76. Programming the Flash

77. Programming the Flash

78. Programming the Flash

79. Programming the Flash

80. PART 2 INSTRUCTION SET AND PROGRAMMING THE 8051

92. POP: The loading the contents of the stack back into a CPU register is called a POP. EX. POP 4 ;POP stack into R4 POP 1 ;POP stack into R1 POP 6 ;POP stack into R6 Start SP = 0B Start SP = 0A Start SP = 09 Start SP = 08 6C 76 F9 54 0B 0A 09 08 6C 76 F9 0B 0A 09 08 6C 76 0B 0A 09 08 6C 0B 0A 09 08 After P0P 3 After POP 5 After POP 2

96. LOGICAL OR OPERATION Cycles/ t-state Bytes Example Operation Mnemonics 2/24 3 ORL 7fh,#n OR each bit of RAM address with the same bit of immediate data n , put the result in RAM ORL add,#n 1/12 2 ORL 90h,A OR each bit of A with the same bit of direct RAM address, put the result in RAM. ORL add,A 1/12 1 ORL A,@R0 OR each bit of A with the same bit of register pointer Rp, put the result in A. ORL A,@Rp 1/12 1 ORL A,R0 OR each bit of A with the same bit of register Rr, put the result in A. ORL A,Rr 1/12 2 ORL A,80h OR each bit of A with the same bit of direct RAM address, put the result in A. ORL A,add 1/12 2 ORL A, #60h OR each bit of A with the same bit of immediate date n, put the result in A. ORL A, #n

97. LOGICAL XOR OPERATION Cycles/ t-state Bytes Example Operation Mnemonics XRL add,#n XRL add,A XRL A,@Rp XRL A,Rr XRL A,add XRL A, #n 2/24 3 XRL 7fh,#n XOR each bit of RAM address with the same bit of immediate data n , put the result in RAM 1/12 2 XRL 90h,A XOR each bit of A with the same bit of direct RAM address, put the result in RAM. 1/12 1 XRL A,@R0 XOR each bit of A with the same bit of register pointer Rp, put the result in A. 1/12 1 XRL A,R0 XOR each bit of A with the same bit of register Rr, put the result in A. 1/12 2 XRL A,80h XOR each bit of A with the same bit of direct RAM address, put the result in A. 1/12 2 XRL A, #60h XOR each bit of A with the same bit of immediate date n, put the result in A.

98. COMPLEMENT OPERATION NOTE: No flags are affected by the byte level logical operations unless the direct RAM address is the PSW. Cycles/ t-state Bytes Example Operation Mnemonics 1/12 1 CPL A Complement each bit of A, CPL A 1/12 1 CLR A Clear each bit of A register to 0. CLR A

100. ROTATE AND SWAP INSTRUCTION SWAP A RRC A RR A RLC A RL A Example Interchange the nibble of register A Rotate the A register and C Flag one bit position to the right Rotate the A register one bit position to the right Rotate the A register and C Flag one bit position to the left Rotate the A register one bit position to the left OPERATION 1 1 1 1 1 Bytes 1/12 RRC A 1/12 SWAP A 1/12 RR A 1/12 RLC A 1/12 RL A Cycles/ t-state MNEMONICS

102. DECREMENTING OPERATION NOTE: No math flags are affected in increment and decrement operation. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 DEC @R1 Subtract a 1 to the content of memory address in Rp DEC @Rp 1/12 2 DEC 20h Subtract a 1 to the content of the direct memory address. DEC add 1/12 1 DEC R4 Subtract a 1 to the Rr register DEC Rr 1/12 1 DEC A subtract a 1 to the A register DEC A

103. ADDITION OPERATION Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 ADD A,@R1 Add A with the content of memory address in Rp, put the result in A. ADD A,@Rp 1/12 2 ADD A, 80h Add A with the content of the direct address, put the result in A. ADD A,add 1/12 1 ADD A,R6 Add A with the content of register Rr, put the result in A. ADD A,Rr 1/12 2 ADD A,#0a0h Add A with the immediate numberr, put the result in A. ADD A,#n

104. ADDITION OPERATION Note: In addition operation all math flag will change. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 ADDC A,@Rp Add A with the content of memory address in Rp and the carry flag, put the result in A. ADDC A,@Rp 1/12 2 ADDC A,add Add A with the content of the direct address and the carry flag, put the result in A. ADDC A,add 1/12 1 ADDC A,Rr Add A with the content of register Rr and the carry flag, put the result in A. ADDC A,Rr 1/12 2 ADDC A,#n Add A with the immediate numberr and the carry flag, put the result in A. ADDC A,#n

105. SUBTRACTION OPERATION NOTE: All math flag will be affected. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 SUBB A, @R1 Subtract the content of the address in Rp and the carry flag from A, put the result in A. SUBB A, @Rp 1/12 1 SUBB A,R0 Subtract Rr and the carry flag from A, put the result in A. SUBB A,Rr 1/12 2 SUBB A,50h Subtract the content of address and the carry flag from A, put the result in A. SUBB A,add 1/12 2 SUBB A,#40h Subtract immediate number n and the carry flag from A, put the result in A. SUBB A,#n

106. ADDITION AND DIVISION OPERATION NOTE: In multiplication and division operation carry flag always set to 0, and the Ov flag will be set. Cycles/ t-state Bytes Example OPERATION MNEMONICS 4/48 1 DIV AB Divide A by B, put the integer part of quotient in register A, and the integer part of the reminder in B DIV AB 4/48 1 MUL AB Multiply A by B, put the lower byte of the product in A, put the higher byte of the product in B. MUL AB

108. BYTE JUMP Jump to the relative address if A is not 0 JNZ radd Jump to the relative address if A is 0 JZ radd Decrement thedirect address by 1 and jump to the relative address if the result is not 0. DJNZ add,radd Decrement the Rn by 1 and jump to the relative address if the result is not 0. DJNZ Rn,radd Compare the contents of the address in Rp with the immediate data, if they are not equal then jump to the relative address CJNE @Rp,#n,radd Compare the Rn with the immediate data, if they are not equal then jump to the relative address CJNE Rn,#n,radd Compare the A with the immediate data, if they are not equal then jump to the relative address CJNE A,#n,radd Compare the A with the address, if they are not equal then jump to the relative address CJNE A,add,radd operation Mnemonics

109. UNCONDITIONAL JUMP Not operation NOP Jump to the relative address SJMP radd Jump to the long range address LJMP ladd(a16) Jump to the short range address AJMP sadd(a11) Jump to the address formed by adding A with DPTR JMP @A+DPTR Operation Mnemonics

110. CALL INSTRUCTION Return from interrupt subroutine. RETI Return from subroutine. RET Call the subroutine located in long address. LCALL ladd(a16) Call the subroutine located in short address. ACALL sadd(a11) OPERATION MNEMONICS

113. First notice that the JZ and JNC instructions both jump forward. The target address for a forward jump is calculated by adding the PC of the following instruction to the second byte of the short jump instruction, which is called the relative address. In line 4 the instruction “JZ NEXT” has opcode of 60 and operand of 03 at the address of 0004 and 0005. The 03 is the relative address, relative to the address of the next instruction INC R0, which is 0006. By adding 0006 to 3, the target address of the label NEXT, which is 0009, is generated. In the same way for line 9, the “JNC OVER” instruction has opcode and operand of 50 and 05 where 50 is the opcode and 05 the relative address. Therefore, 05 is added to 000D, the address of instruction “CLR A”, giving 12H, the address of label OVER. (b) Solution: In that program list, “JNC AGAIN” has opcode 50 and relative address F2H. When the relative address of F2H is added to 15H, the address of the instruction below the jump, we have 15H +F2H= 07 (the carry is dropped). Notice that 07 is the address of label AGAIN. Look also at “SJMP HERE”, which has 80 FE for the opcode and relative address, respectively. The PC of the following instruction, 0017H, is added to FEH, the relative address, to get 0015H, address of the HERE label (17H+FEH). Notice that FEH is –2 and 17H+(-2)= 15H.

118. CPU to execute an instruction takes a certain number of clock cycles. These clock cycles are referred as ‘Machine Cycles’. The length of the machine cycle depends on the frequency of the crystal oscillator. One machine cycle lasts for 12 oscillator periods. Therefore, to calculate the machine cycle, we take 1/12 of the crystal frequency, then take the inverse. Ex.: for 16 MHz crystal oscillator calculation machine cycle is as followed: 16MHz/12=1.333MHz Machine cycle=1/1.333MHz=0.75microseconds TIME DELAY GENERATION AND CALCULATION

120. Example1: Find the size of the delay in the following program, if the crystal frequency is 11.0592 MHz. MOV A,#55H AGAIN: MOV P1,A ACALL DELAY CPL A SJMP AGAIN ;……………..Time delay DELAY: MOV R3,#200 HERE: DJNZ R3,HERE RET Solution: From Table A-1 in Appendix A, the following machine cycles for each instruction of the DELAY subroutine. Machine cycle DELAY: MOV R3,#200 1 HERE: DJNZ R3,HERE 2 RET 1 Therefore, the total time delay=[(200*2)+1+1]*1.085  s=436.17  s.

121. Example 2: For a machine cycle of 1.085  s, find the time delay in the following subroutine. DELAY: Machine cycle MOV R2,#200 1 AGAIN: MOV R3,#250 1 HERE: NOP 1 NOP 1 DJNZ R3,HERE 2 DJNZ R2,AGAIN 2 RET 1 For the HERE loop, (4*250)1.085  s= 1085  s. The AGAIN loop repeats the HERE loop 200 times; therefore, 200*1085  s= 217000, if we do not include the overhead. However, the instructions “MOV R3,#250” and “DJNZ R2,AGAIN” at the beginning and end of the AGAIN loop add (3*200*1.085  s)= 651  s to the time delay. As a result we have 217000+651= 217651  s= 217.651 milliseconds for total time delay associated with the above DELAY subroutine.

123. TIMER/COUNTER Timer: To generate time delay. Counter : To count any external event. Both timer0 & timer1 registers are 16 bit wide. 8051 has 8 – bit architecture. So 16 – bit timer is accessed as two separate registers of low byte (TL0/TL1) & high byte (TH0/TH1). clock source of timer is the 1/12 of the crystal frequency.

125. XTAL oscillator 12 T0 pin Pin 3.4 C / T = 0 C / T = 1 TR0 Gate INT0 pin Pin 3.2 Timer/counter 0 When GATE=1 in TMOD

126. TF1 TCON.7 Timer 1 overflow flag.Set by hardware when timer/counter 1 overflows.Cleared by hardware as the processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit.Set by software to turn timer/counter 1on/off. TF0 TCON.5 Timer 0 overflow flag.Set by hardware when timer/counter 0 overflows.Cleared by hardware as the processor vectors to the interrupt service routine. TR0 TCON.4 Timer 0 run control bit.Set by software to turn timer/counter 0 on/off. IE1 TCON.3 External interrupt 1 edge flag.Set by CPU when the external interrupt edge(H-to-L transition) is detected.Cleared by CPU when the interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit.Set/cleared by software to specify falling edge/low-level triggered external interrupt. IE0 TCON.1 External interrupt 0 edge flag.Set by CPU when the external interrupt edge(H-to-L transition) is detected.Cleared by CPU when the interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit.Set/cleared by software to specify falling edge/low-level triggered external interrupt. IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1 (MSB) (LSB) TIMER CONTROL REGISTER (TCON)

127. MODE 1 16 BIT TIMER/COUNTER MODE 0 13 BIT TIMER/COUNTER XTAL oscillator 12 THX TLX TF TF goes high overflow When FFFF 0 flag C / T = 0 TR XTAL oscillator 12 THX(8 BIT) TLX(5 BIT) TF TF goes high overflow When FF1F 0 flag C / T = 0 TR

130. Delay=(256-TLX)X12/ F osc TL0 (8BIT) TF0 TH0 (8 BITS) TF1 INTERRUPT INTERRUPT PULSE INPUT F/12 TR1 BIT IN TCON MODE 3, TWO 8 BIT TIMER USING TIMER 0 MODE2 AUTO RELOAD OF TL FROM TH XTAL oscillator 12 TL TF TF goes high When FF 0 C / T = 0 TR Overflow flag TH reload

132. Find the delay generated by timer 0 in the following code, using both of the methods of Figure 9-4. Do not include the overhead due to instructions. CLR P2 . 3 ; clear P2 . 3 MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode) HERE: MOV TL0, #3EH ; TL0 = 3E, low byte MOV T01, #0B8H ; TH0 = B8, high byte SETB P2 . 3 ; set high P2 . 3 SETB TR0 ; start the timer 0 AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0 CLR TR0 ; stop the timer 0 CLR TF0 ; clear timer 0 flag for next round CLR P2 . 3 Solution: (a) (FFFF – B83E + 1) = 47C2H = 18370 in decimal and 18370*1.085  s = 19.93145 ms. (b) Since TH – TL = B83EH = 47166 (in decimal) we have 65536 – 47166 = 18370. This means that the timer counts from B83EH to FFFF. This plus rolling over to 0 goes through a total of 18370 clock cycles, where each clock is 1. 085  s in duration. Therefore, we have 18370*1.085  s =19.93145 ms as the width of the pulse. Modify TL and TH in Example above to get the largest time delay possible. Find the delay in ms. In your calculation, exclude the overhead due to the instructions in the loop. Solution: To get the largest delay we make TL and TH both 0. This will count up from 0000 to FFFFH and then roll over to zero. CLR P2 . 3 ; clear P2 . 3 MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode) HERE: MOV TL0, # 0 ; TL0 = 0, the low byte MOV TH0, # 0 ; TH0 =0, the high byte SETB P2 . 3 ; set high P2 . 3 SETB TR0 ; start timer 0 AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0 CLR TR0 ; stop timer 0 CLR TF0 ; clear timer 0 flag CLR P2 . 3 Making TH and TL both zero means that the timer will count from 0000 to FFFF, and then roll over to raise the TF flag. As a result, it goes through a total of 65536 states. Therefore, we have delay = (65536-0) x 1. 085  s = 71. 1065 ms.

134. Counters: When C/T=1, in TMOD register the timer is used as a counter and gets its pulses from pin 14 and 15.This pins are called T0 and T1& belongs to port 3. EX. Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses and display the state of the TL1 count on P2. MOV TMOD,#01100000B MOV TH1,#0 SETB P3.5 AGAIN SETB TR1 BACK MOV A,TL1 MOV P2,A JNB TF1,BACK CLR TR1 CLR TF1 SJMP AGAIN

135. TH0 TL0 TF0 TR0 Timer 0 External Input Pin 3.4 C / T = 1 Overflow flag TF0 goes high When FFFF 0 Timer/Counter 0 with External Input (Mode 1) TL0 TF0 TR0 Timer 0 External Input Pin 3.4 C / T = 1 Overflow flag TF0 goes high When FF 0 Timer/Counter 0 with External Input (Mode 2) TH0 reload

136. Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses and display the state of the TL1 count on P2. Solution: MOV TMOD, #0110000B ; counter 1, mode 2, C/T= 1; external pulses MOV TH1, # 0 ; clear TH1 SETB P3 . 5 ; make T1 input AGAIN: SETB TR1 ; start the counter BACK: MOV A, TL1 ; get copy of count TL1 MOV P2, A ; display it on port 2 JNB TF1, BACK ;keep doing it if TF =0 CLR TR1 ; stop the counter CLR TF1 ; make TF=0 SJMP AGAIN ; keep doing it Notice in the above program the role of the instruction “SETB P3 . 5”. Since ports are set up for output when the 8051 is powered up, we make P3 . 5 an input port by making it high. In other words. We must configured (set high) the T1 pin (pin P3 . 5) to allow pulses to be fed into it. P2 To LEDs P3.5 T1 8051 P2 is connected to 8 LEDs And input T0 to pulses.

138. Transmitter Transmitter Receiver Transmitter Receiver Receiver Receiver Transmitter Receiver Transmitter Simplex Half Duplex Full Duplex Simplex, Half & full duplex Transfers

140. 8051 CONNECTION TO RS232: RS232 is the most widely used serial I/O interfacing standard. In RS232 1 is represented by –3 to –25 V & 0 is represented by +3 to +25V. For conversion from TTL to RS232 standard, MAX232 IC chip is used. 1 3 4 5 T1 IN R1 OUT T2 IN R2 OUT + C1 C2 + 11 12 10 9 TTL SIDE 15 RS232 side 16 2 6 + C3 + 14 13 7 8 8051 P3.1 TXD P3.0 RXD 10 12 11 11 MAX232 14 13 2 3 DB-9 5 C4

141. SERIAL COMMUNICATION WITH 8051: Baud rate is to be selected with the help of Timer 1 with auto reload mode. Clock for 8051 UART circuitry: Divide machine cycle by 32 before it is used by timer 1 to set the baud rate. For various baud rates, TH1 must be loaded with the following values: (XTAL = 11.0592 MHz), Why TH1? BAUD RATE TH1 (decimal) TH1(hex) 9600 -3 FD 4800 -6 FA 2400 -12 F4 1200 -24 E8

142. SBUF register: SBUF is an 8-bit register used solely for serial communication in the 8051.For a byte of data to be transferred via the TXD line, it must be placed in the SBUF register.Similarly it holds the byte of data received by 8051’s RXD line. SCON register: The SCON register is an 8-bit register used to program the start bit,stop bit,and data bits of data framing. R1 T1 RB8 TB8 REN SM2 SM1 SM0 SM0 SCON.7 Serial port mode specifier SM1 SCON.6 Serial port mode specifier SM2 SCON.5 used in mode 2 & 3,set to 1 when bit 9 of received data is 1 and a interrupt is generated. REN SCON.4 Set/cleared by software to enable/disable reception. TB8 SCON.3 transmitted bit 8 in modes 2 & 3, set/cleared by program RB8 SCON.2 received bit 8 in mode 2 & 3, stop bit in mode 1, not used in mode 0. T1 SCON.1 Transmit interrupt flag.Set by hardware at the beginning of the stop bit in mode 1. Must be cleared by software. R1 SCON.0 Receive interrupt flag.Set by hardware halfway through the stop bit time in mode 1.Must be cleared by software.

143. SM0 SM1 0 0 : Serial mode 0, shift register, baud = f/12 0 1 : Serial mode 1, 8 bit UART, baud = variable 1 0 : 9 bit UART, baud = f/32 or f/64 1 1 : 9 bit UART, baud = variable REN: receive enable bit (SCON.4) When it is high, it allows the 8051 to receive data on the RXD pin, TI: Transmit interrupt (SCON.1) When 8051 finishes the transfer of 8 bit character, TI flag will be high to indicate that it is ready to transfer another byte. RI: Receive interrupt (SCON.0) When 8051 receives data, it places the byte in SBUF register (excluding start and stop bit) and raises RI flag to indicate that a byte is in SBUF to pick up.

148. With XTAL = 11.0592 MHz. Find the TH1 value needed to have the following baud rates. (a) 9600, (b) 2400, (c) 1200 Solutions: With XTAL = 11.0592 MHz, we have: The machine cycle frequency of the 8051 = 11.0592 MHz / 12 = 921.6 kHz, and 921.6 kHz / 32 = 28,800 Hz is the frequency provided by UART to timer 1 to set baud rate. (a) 28,800 / 3 = 9600 where – 3 = FD (hex) is loaded into TH1 (b) 28,800 / 12 = 2400 where – 12 = F4 (hex) is loaded into TH1 © 28,800 / 24 = 1200 where – 24 = E8 (hex) is loaded into TH1 Notice that dividing 1/12 th of the crystal frequency by 32 is the default value upon activation of the 8051RESET pin. We can change this default setting. XTAL oscillator 12 32 By UART Machine cycle freq. 921.6 kHz 28800 Hz To timer to set the baud rate

149. Program for the 8051 to transfer letter “’A” serially at 4800 baud rate. MOV TMOD, # 20H ;timer1, mode 2 MOV TH1,# 0FAh ; MOV SCON,# 50h ; 8bit, 1 stop bit, REN enabled SETB TR1 ; MOV SBUF,#”A” HERE: JNB T1, HERE CLR TI 1. Write a program to transfer the message “FINE” serially at 2400 baud rate, 8 bit data, 1 stop bit. 2. Program 8051 to receive bytes of data serially and put them in P1. Set the baud rate 2400, 8-bit data, 1 stop bit.

151. Steps in executing interrupt: After activation of an interrupt, the micro controller goes through the following steps: 1. Finishes the instruction it is executing and saves the address of the next instruction on the stack. 2. Saves the current status of all the interrupts. 3. Jumps to a fixed location in memory called the interrupt vector table that holds the address of the interrupt service routine. 4. The micro controller gets the address of the ISR from the interrupt vector table, jumps to it and starts to execute it. 5. After executing RETI instruction, the micro-controller returns to the place from where it was interrupted and starts to execute from that address.

153. EX0 ET0 EX1 ET1 ES ET2 --- EA D7 D0 IE REGISTER EA IE.7 Disable all interrupts.If EA=0, no interrupt is acknowledged.If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. -- IE.6 Not implemented, reserved for future use.* ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952). ES IE.4 Enables or disables the serial port interrupt. ET1 IE.3 Enables or disables timer 1overflow interrupt. EX1 IE.2 Enables or disables external interrupt 1. ET0 IE.1 Enables or disables timer 0 overflow interrupt. EX0 IE.0 Enables or disables external interrupt 0. * User software should not write 1s to reserved bits.These bits may be used in future Flash micro controllers to invoke new features.

154. 0023 Serial COM interrupt (R1 and T1) 001B Timer 1 interrupt (TF1) P3.3 (13) 0013 External hardware interrupt 1 (INT1) 000B Timer 0 interrupt (TF0) P3.2 (12) 0003 External hardware interrupt 0 (INT0) 9 0000 Reset pin ROM Location (Hex) Interrupt Interrupt Vector Table for the 8051

155. Write a program to create a square wave that has a high portion of 1085 micro second and a low portion of 15 micro second. Use Timer1. ORG 0000H LJMP MAIN ORG 001BH LJMP ISR_T1 ORG 0040H MAIN: MOV TMOD,#10H ;timer1, mode 1 MOV P0,#0FFH MOV TL1,#18H MOV TH1,#0FCH MOV IE,#88H ;enable timer 1 interrupt SETB TR1 BACK: MOV A,P0 MOV P1,A SJMP BACK ISR_T1: CLR TR1 CLR P2.1 ; start of low portion MOV R2,#4H HERE: DJNZ R2, HERE MOV TL1, #18H MOV TH1,#0FCH SETB TR1 SETB P2.1 RET1 END Write a program to generate a square wave of 100 Hz frequency on pin 1.4 using interrupt for timer 0.XTAL = 12 MHz.

156. External interrupt: There are two activation levels for the external hardware interrupts. 1.Level triggered: In level triggered mode, INT0 and INT1 pins are normally high and if a low level signal is applied to them, it triggers the interrupt. Must be held in low state until the start of execution of ISR. Must be removed before RETI. IE0 (TCON.1) 0003 1 0 Level-triggered INT0 (Pin 3.2) IE1 (TCON.3) 0013 1 0 Level-triggered INT1 (Pin 3.3) 0 1 Edge-triggered Edge-triggered IT0 IT1

157. IT0 TCON.0 Interrupt 0 type control bit IE0 TCON.1 Interrupt 0 edge flag IT1 TCON.2 Interrupt 1 type control bit IE1 TCON.3 Interrupt 1 edge flag TR0 TCON.4 Timer 0 run control bit TF0 TCON.5 Timer 0 overflow flag TR1 TCON.6 Timer 1 run control bit TF1 TCON.7 Timer 1 overflow flag Edge triggered: To make the interrupts edge triggered interrupts,we must program the bits (IT0 AND IT1) of the TCON register. For edge triggered interrupt, source must be held high at least one m/c cycle and then held low for at least one m/c cycle. IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1 D7 D0

158. Problem1: Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low , it should turn on an LED which is connected to pin P1.3. It should stay on for a fraction of a second. Problem2: Write the same program using edge triggered interrupt. What difference will you observe if you run the two programs using a switch.

159. SERIAL COMMUNICATION INTERRUPT: Serial interrupt is invoked using TI or RI flags and interrupt vector table at 0023h. *Clear RI/TI flag before RETI instruction. Problem: Write a program in which the 8051 gets data from P1 and sends it to P2 continuously while incoming data from serial port is sent to P0. XTAL = 12 MHz, baud rate 9600. TI RI 0023H Serial interrupt is invoked by TI or RI flags

160. IP REGISTER (bit addressable) PT2: Timer 2 int. priority bit PS: Serial port int. priority bit PT1: Timer 1 int. priority bit PX1: External int.1 priority bit PT0: Timer 0 int. priority bit PX0: External int.0 priority bit Problem: To make timer int. 1 highest priority, what will be the value in IP register. What will be the sequence in which the interrupts are serviced. PX0 PT0 PX1 PT1 PS PT2 ----- -----

163. 8 2 5 5 A PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Interfacing with 8255A

165. RS, register select: If RS=0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. if RS=1 the data register is selected, allowing the user to send data to be displayed on the LCD. R/W, read/write: R/W=1 when reading; R/W=0 when writing. E, enable: When data is supplied to data pins, a high-to-low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins. This pulse be a minimum of 450 ns wide. D0 – D7: To display letters and numbers, we send ASCII codes for the letters A – Z, and a – z, and numbers 0 – 9 to these pins while making RS=1. We also use RS=0 to check the busy flag bit to see if the LCD is ready to receive information. It is recommended to writing any data to the LCD.

166. The 8 bit data bus DB7 14 The 8 bit data bus DB6 13 The 8 bit data bus DB5 12 The 8 bit data bus DB4 11 The 8 bit data bus DB3 10 The 8 bit data bus DB2 9 The 8 bit data bus DB1 8 The 8 bit data bus DBO 7 Enable (active high) E 6 R/W=0 write, R/W=1 read R/W 5 R=0 command register, R=1 data register RS 4 Power supply to control contrast Vee 3 +5v power supply Vcc 2 Ground Vss 1 DESCRIPTION SYMBOL PIN

167. 80h Force cursor to beginning of 1 st line C0h force cursor to beginning of 2 nd line B/F=1/0 busy/notbusy Current address BF 1 0 DL=1/0;8/4 bit per character N=1/0; 2/1 rows of character F=1/0; 5x10/5x7 dots per character 0 0 F N DL 1 0 0 0 0 S/C=1/0 screen/cursor R/L=1/0; shift one space R/L 0 0 R/L S/C 1 0 0 0 0 0 D=1/0; screen on/off, C=1/0; cursor on/off, B=1/0;blink/notblink B C D 1 0 0 0 0 0 0 S=1/0;shift screen /cursor I/O=1/0; cursor R/L, screen L/R S I/O 1 0 0 0 0 0 0 0 clear home curser only 0 1 0 0 0 0 0 0 0 0 Clear LCD and memory home curser 1 0 0 0 0 0 0 0 0 0 FUNCTION D0 D1 D2 D3 D4 D5 D6 D7 R/W RS

171. INTERFACING A STEPPER MOTOR 31 A 40 9 T 8 9 P2.3 18 C P2.4 5 P2.5 19 1 P2.6 LS373 LATCH ULN 2803A STEPPER MOTOR +12V +5V

172. Full step operation with one coil energized Full step operation with two coil energized 1 0 0 0 4 0 1 0 0 3 0 0 1 0 2 0 0 0 1 1 D C B A STEP 1 0 0 1 4 1 1 0 0 3 0 1 1 0 2 0 0 1 1 1 D C B A STEP

173. Half step operation with two coil energized 1 0 0 1 8 1 0 0 0 7 1 1 0 0 6 0 1 0 0 5 0 1 1 0 4 0 0 1 0 3 0 0 1 1 2 0 0 0 1 1 D C B A STEP

178. Pin Description

180. Analog Channel Selection

181. Timing Diagram

182. Interfacing 8051 With ADC0809

186. Interfacing with Seven segment decoder a b c d e f g Segment pattern a b c d e f g Common cathode Segment circuit

187. Connection with 8051(CA)

188. Connection with 8051(CC)

189. 67 98 9 7F 80 8 07 F8 7 7D 82 6 6D 92 5 66 99 4 4F B0 3 5B A4 2 06 F9 1 3F C0 0 Data for CC .gfedcba(d7-d0) Data for CA .gfedcba(d7-d0) Display

194. Seven-segment Display circuit Used for Svnseg Program +5V a b c d e f g Display 1 a b c d e f g Display 1 a b c d e f g Display 1 a b c d e f g Display 1 Q a Q b Q c Q d Q e Q f Q g Chose R for brightness Q 1 Q 2 Q 3 Q 4 cc cc cc cc 7 P1.6 6 P1.5 5 P1.4 4 P1.3 3 P1.2 2 P1.1 1 P1.0 12 P3.2 13 P3.3 14 P3.4 15 P3.5 Q 1 – Q 4 B > 1000 8031

196. THANK YOU