SlideShare a Scribd company logo
1 of 24
Download to read offline
Sequential circuits
• A sequential circuit is consists of combinational logic, 
feedback path and employs some memory elements 
Feedback path 
Sequential circuit= Combinational logic + Memory 
Elements 
Present state 
Next state
• The memory element is a device which can 
remember value indefinitely, or change value on 
command from its inputs. 
• The memory element also has a clock input which 
provides timing for changing states. 
• The feedback path is required for the circuit to 
have memory.
• State changes are controlled by clocks. 
A “clock” is a special circuit that sends electrical 
pulses through a circuit. 
• Clocks produce electrical waveforms in generally 
some form of square wave 
• Circuits can change state on the rising edge, falling 
edge, or when the clock pulse reaches its highest 
voltage.
Sequential circuits
• are storage elements that operate with 
signal levels (rather than signal transitions) 
• useful for storing binary information and for 
the design of asynchronous sequential 
circuits 
• are the building blocks of flip-flops
•The SR latch is a circuit with two 
cross-coupled NOR gates or two 
cross-coupled NAND gates, 
•The two inputs are labeled S for set 
and R for reset.
Sequential circuits
• when Q = 1 and Q’ = 0, the latch is said to 
be in the set state 
• S=HIGH (and R=LOW) 
R 
S 
Q’ 
Q 
S R Q Q' 
1 0 1 0 initial 
0 0 1 0 (afer S=1, R=0) 
0 1 0 1 
0 0 0 1 (after S=0, R=1) 
1 1 0 0 invalid! 
0 
1 
1 
0
• The inputs must go back to their normal conditions 
(S=0, R=0) before any changes occur 
0 
0 
1 
0 
R 
S 
Q 
Q' 
S R Q Q' 
1 0 1 0 initial 
0 0 1 0 (afer S=1, R=0) 
0 1 0 1 
0 0 0 1 (after S=0, R=1) 
1 1 0 0 invalid!
1 
0 
• When Q = 0 and Q’ = 1, it is in the 
0 
1 
R 
S 
Q 
Q' 
S R Q Q' 
1 0 1 0 initial 
0 0 1 0 (afer S=1, R=0) 
0 1 0 1 
0 0 0 1 (after S=0, R=1) 
1 1 0 0 invalid! 
reset state 
• S=LOW (and R=HIGH)
• The inputs must go back to their normal conditions 
(S=0, R=0) before any changes occur 
R 
S 
Q 
Q' 
S R Q Q' 
1 0 1 0 initial 
0 0 1 0 (afer S=1, R=0) 
0 1 0 1 
0 0 0 1 (after S=0, R=1) 
1 1 0 0 invalid! 
0 
0 
0 
1
If both inputs HIGH a Q and Q' both 
R 
S 
Q 
Q' 
S R Q Q' 
1 0 1 0 initial 
0 0 1 0 (afer S=1, R=0) 
0 1 0 1 
0 0 0 1 (after S=0, R=1) 
1 1 0 0 invalid! 
1 
1 
0 
0 
LOW (invalid)!
Sequential circuits
• when Q = 0 and Q’ = 1, the latch is said to 
be in the set state 
• R=LOW (and S=HIGH) 
S 
R 
Q 
Q' 
S R Q Q' 
1 0 0 1 initial 
1 1 0 1 (afer S=1, R=0) 
0 1 1 0 
1 1 1 0 (after S=0, R=1) 
0 0 1 1 invalid! 
1 
0 
0 
1
• The inputs must go back to their normal conditions 
(S=1, R=1)before any changes occur 
S 
R 
Q 
Q' 
S R Q Q' 
1 0 0 1 initial 
1 1 0 1 (afer S=1, R=0) 
0 1 1 0 
1 1 1 0 (after S=0, R=1) 
0 0 1 1 invalid! 
1 
0 
1 
1
• When Q = 0 and Q’ = 1, it is in the 
S 
R 
Q 
Q' 
S R Q Q' 
1 0 0 1 initial 
1 1 0 1 (afer S=1, R=0) 
0 1 1 0 
1 1 1 0 (after S=0, R=1) 
0 0 1 1 invalid! 
0 
1 
1 
0 
reset state 
• R=LOW (and S=HIGH)
• The inputs must go back to their normal conditions 
(S=1, R=1)before any changes occur 
S 
R 
Q 
Q' 
S R Q Q' 
1 0 0 1 initial 
1 1 0 1 (afer S=1, R=0) 
0 1 1 0 
1 1 1 0 (after S=0, R=1) 
0 0 1 1 invalid! 
1 
1 
1 
0
If both inputs LOW a Q and Q' both 
S 
R 
Q 
Q' 
S R Q Q' 
1 0 0 1 initial 
1 1 0 1 (afer S=1, R=0) 
0 1 1 0 
1 1 1 0 (after S=0, R=1) 
0 0 1 1 invalid! 
0 
1 
0 
1 
LOW (invalid)!
Sequential circuits
Sequential circuits
• Ensure that inputs S and R are never equal to 1 at the 
same time. 
• has only two inputs: D (data) and En (enable)
When EN is HIGH, 
D=HIGH  latch is SET 
D=LOW  latch is RESET 
Hence when EN is HIGH, Q ‘follows’ the D 
(data) input. 
Characteristic table: 
EN D Q 
1 0 0 Reset 
1 1 1 Set 
0 X Q No change
Sequential circuits

More Related Content

What's hot

Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic designNallapati Anindra
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliDipayan Sarkar
 
Sequential circuits in Digital Electronics
Sequential circuits in Digital ElectronicsSequential circuits in Digital Electronics
Sequential circuits in Digital ElectronicsVinoth Loganathan
 
Lecture 5 Synchronous Sequential Logic
Lecture 5 Synchronous Sequential LogicLecture 5 Synchronous Sequential Logic
Lecture 5 Synchronous Sequential LogicJames Evangelos
 
Sequential circuit
Sequential circuitSequential circuit
Sequential circuitBrenda Debra
 
Combinational Circuits & Sequential Circuits
Combinational Circuits & Sequential CircuitsCombinational Circuits & Sequential Circuits
Combinational Circuits & Sequential Circuitsgourav kottawar
 
All about Sequential circuits DLD.
All about Sequential circuits DLD.All about Sequential circuits DLD.
All about Sequential circuits DLD.Zain Jafri
 
Registers-shift register
Registers-shift registerRegisters-shift register
Registers-shift registerBilawal Fiaz
 
Pin digram of 8086
Pin digram of 8086Pin digram of 8086
Pin digram of 8086RJ
 

What's hot (20)

Counters
CountersCounters
Counters
 
Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic design
 
Sequential circuits
Sequential circuitsSequential circuits
Sequential circuits
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N Ali
 
Sequential circuits in Digital Electronics
Sequential circuits in Digital ElectronicsSequential circuits in Digital Electronics
Sequential circuits in Digital Electronics
 
Lecture 5 Synchronous Sequential Logic
Lecture 5 Synchronous Sequential LogicLecture 5 Synchronous Sequential Logic
Lecture 5 Synchronous Sequential Logic
 
Basic Logic gates
Basic Logic gatesBasic Logic gates
Basic Logic gates
 
Registers siso, sipo
Registers siso, sipoRegisters siso, sipo
Registers siso, sipo
 
SEQUENTIAL CIRCUITS [Flip-flops and Latches]
SEQUENTIAL CIRCUITS [Flip-flops and Latches]SEQUENTIAL CIRCUITS [Flip-flops and Latches]
SEQUENTIAL CIRCUITS [Flip-flops and Latches]
 
Sequential circuit
Sequential circuitSequential circuit
Sequential circuit
 
Chapter 6: Sequential Logic
Chapter 6: Sequential LogicChapter 6: Sequential Logic
Chapter 6: Sequential Logic
 
Flip Flop
Flip FlopFlip Flop
Flip Flop
 
Combinational Circuits & Sequential Circuits
Combinational Circuits & Sequential CircuitsCombinational Circuits & Sequential Circuits
Combinational Circuits & Sequential Circuits
 
All about Sequential circuits DLD.
All about Sequential circuits DLD.All about Sequential circuits DLD.
All about Sequential circuits DLD.
 
Flip flop
Flip flopFlip flop
Flip flop
 
Registers-shift register
Registers-shift registerRegisters-shift register
Registers-shift register
 
Nand and nor
Nand and norNand and nor
Nand and nor
 
Microcontroller 8051
Microcontroller 8051Microcontroller 8051
Microcontroller 8051
 
Counters
Counters Counters
Counters
 
Pin digram of 8086
Pin digram of 8086Pin digram of 8086
Pin digram of 8086
 

Viewers also liked

Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits DrSonali Vyas
 
Demultiplexer presentation
Demultiplexer presentationDemultiplexer presentation
Demultiplexer presentationShaikat Saha
 
1 Multiplexer
1 Multiplexer1 Multiplexer
1 Multiplexerna491
 
Multiplexer
Multiplexer Multiplexer
Multiplexer Gaditek
 
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGNSEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGNQAU ISLAMABAD,PAKISTAN
 
Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Abhilash Nair
 
Demultiplexer
DemultiplexerDemultiplexer
DemultiplexerTech_MX
 
Unit 3
Unit  3Unit  3
Unit 3siddr
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuitsSARITHA REDDY
 
Flip flop’s state tables & diagrams
Flip flop’s state tables & diagramsFlip flop’s state tables & diagrams
Flip flop’s state tables & diagramsSunny Khatana
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic CircuitRamasubbu .P
 
Sequential circuit design
Sequential circuit designSequential circuit design
Sequential circuit designSatya P. Joshi
 

Viewers also liked (20)

Demultiplexers
DemultiplexersDemultiplexers
Demultiplexers
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits
 
Multiplexers
MultiplexersMultiplexers
Multiplexers
 
Demultiplexer presentation
Demultiplexer presentationDemultiplexer presentation
Demultiplexer presentation
 
1 Multiplexer
1 Multiplexer1 Multiplexer
1 Multiplexer
 
Digital 1 8
Digital 1 8Digital 1 8
Digital 1 8
 
Multiplexer
Multiplexer Multiplexer
Multiplexer
 
Multiplexer
MultiplexerMultiplexer
Multiplexer
 
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGNSEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN
 
Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)
 
Demultiplexer
DemultiplexerDemultiplexer
Demultiplexer
 
Unit 3
Unit  3Unit  3
Unit 3
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
multiplexer and d-multiplexer
multiplexer and d-multiplexermultiplexer and d-multiplexer
multiplexer and d-multiplexer
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Flip flop’s state tables & diagrams
Flip flop’s state tables & diagramsFlip flop’s state tables & diagrams
Flip flop’s state tables & diagrams
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic Circuit
 
Flipflop
FlipflopFlipflop
Flipflop
 
Multiplexers & Demultiplexers
Multiplexers & DemultiplexersMultiplexers & Demultiplexers
Multiplexers & Demultiplexers
 
Sequential circuit design
Sequential circuit designSequential circuit design
Sequential circuit design
 

Similar to Sequential circuits

Sequentialcircuits
SequentialcircuitsSequentialcircuits
SequentialcircuitsRaghu Vamsi
 
IS 151 Lecture 10
IS 151 Lecture 10IS 151 Lecture 10
IS 151 Lecture 10wajanga
 
best slides latches.pdf
best slides latches.pdfbest slides latches.pdf
best slides latches.pdfAreebaShoukat4
 
Digital Electronics Unit_3.pptx
Digital Electronics Unit_3.pptxDigital Electronics Unit_3.pptx
Digital Electronics Unit_3.pptxThapar Institute
 
UNIT - III.pptx
UNIT - III.pptxUNIT - III.pptx
UNIT - III.pptxamudhak10
 
B sc cs i bo-de u-iv sequential circuit
B sc cs i bo-de u-iv sequential circuitB sc cs i bo-de u-iv sequential circuit
B sc cs i bo-de u-iv sequential circuitRai University
 
Digital Electronics R-S, J-K flip flop etc.pptx
Digital Electronics R-S, J-K  flip flop etc.pptxDigital Electronics R-S, J-K  flip flop etc.pptx
Digital Electronics R-S, J-K flip flop etc.pptxProfVilasShamraoPati
 
Computer Oragnization Flipflops
Computer Oragnization FlipflopsComputer Oragnization Flipflops
Computer Oragnization FlipflopsVanitha Chandru
 
08 Latches and Flipflops.pdf
08 Latches and Flipflops.pdf08 Latches and Flipflops.pdf
08 Latches and Flipflops.pdfDSOOP
 
Flipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsFlipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsstudent
 
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docx
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docxLab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docx
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docxDIPESH30
 
Logic Design - Chapter 6: Flip Flops
Logic Design - Chapter 6: Flip FlopsLogic Design - Chapter 6: Flip Flops
Logic Design - Chapter 6: Flip FlopsGouda Mando
 
Latch Introduction & RS Latch
Latch Introduction &  RS LatchLatch Introduction &  RS Latch
Latch Introduction & RS LatchEasy n Inspire L
 

Similar to Sequential circuits (20)

Sequentialcircuits
SequentialcircuitsSequentialcircuits
Sequentialcircuits
 
Sequential
SequentialSequential
Sequential
 
IS 151 Lecture 10
IS 151 Lecture 10IS 151 Lecture 10
IS 151 Lecture 10
 
best slides latches.pdf
best slides latches.pdfbest slides latches.pdf
best slides latches.pdf
 
Digital Electronics Unit_3.pptx
Digital Electronics Unit_3.pptxDigital Electronics Unit_3.pptx
Digital Electronics Unit_3.pptx
 
Flipflop r012
Flipflop   r012Flipflop   r012
Flipflop r012
 
12 latches
12 latches12 latches
12 latches
 
UNIT - III.pptx
UNIT - III.pptxUNIT - III.pptx
UNIT - III.pptx
 
B sc cs i bo-de u-iv sequential circuit
B sc cs i bo-de u-iv sequential circuitB sc cs i bo-de u-iv sequential circuit
B sc cs i bo-de u-iv sequential circuit
 
Digital Electronics R-S, J-K flip flop etc.pptx
Digital Electronics R-S, J-K  flip flop etc.pptxDigital Electronics R-S, J-K  flip flop etc.pptx
Digital Electronics R-S, J-K flip flop etc.pptx
 
Computer Oragnization Flipflops
Computer Oragnization FlipflopsComputer Oragnization Flipflops
Computer Oragnization Flipflops
 
08 Latches and Flipflops.pdf
08 Latches and Flipflops.pdf08 Latches and Flipflops.pdf
08 Latches and Flipflops.pdf
 
lec7.ppt
lec7.pptlec7.ppt
lec7.ppt
 
Flipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflopsFlipflops and Excitation tables of flipflops
Flipflops and Excitation tables of flipflops
 
Sr Latch or Flip Flop
Sr Latch or Flip FlopSr Latch or Flip Flop
Sr Latch or Flip Flop
 
S-R Latch
S-R LatchS-R Latch
S-R Latch
 
Flip flops
Flip flopsFlip flops
Flip flops
 
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docx
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docxLab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docx
Lab 12 – Latches and Flip-Flops Mugisha OmaryLab 12 .docx
 
Logic Design - Chapter 6: Flip Flops
Logic Design - Chapter 6: Flip FlopsLogic Design - Chapter 6: Flip Flops
Logic Design - Chapter 6: Flip Flops
 
Latch Introduction & RS Latch
Latch Introduction &  RS LatchLatch Introduction &  RS Latch
Latch Introduction & RS Latch
 

Sequential circuits

  • 2. • A sequential circuit is consists of combinational logic, feedback path and employs some memory elements Feedback path Sequential circuit= Combinational logic + Memory Elements Present state Next state
  • 3. • The memory element is a device which can remember value indefinitely, or change value on command from its inputs. • The memory element also has a clock input which provides timing for changing states. • The feedback path is required for the circuit to have memory.
  • 4. • State changes are controlled by clocks. A “clock” is a special circuit that sends electrical pulses through a circuit. • Clocks produce electrical waveforms in generally some form of square wave • Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.
  • 6. • are storage elements that operate with signal levels (rather than signal transitions) • useful for storing binary information and for the design of asynchronous sequential circuits • are the building blocks of flip-flops
  • 7. •The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, •The two inputs are labeled S for set and R for reset.
  • 9. • when Q = 1 and Q’ = 0, the latch is said to be in the set state • S=HIGH (and R=LOW) R S Q’ Q S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid! 0 1 1 0
  • 10. • The inputs must go back to their normal conditions (S=0, R=0) before any changes occur 0 0 1 0 R S Q Q' S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid!
  • 11. 1 0 • When Q = 0 and Q’ = 1, it is in the 0 1 R S Q Q' S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid! reset state • S=LOW (and R=HIGH)
  • 12. • The inputs must go back to their normal conditions (S=0, R=0) before any changes occur R S Q Q' S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid! 0 0 0 1
  • 13. If both inputs HIGH a Q and Q' both R S Q Q' S R Q Q' 1 0 1 0 initial 0 0 1 0 (afer S=1, R=0) 0 1 0 1 0 0 0 1 (after S=0, R=1) 1 1 0 0 invalid! 1 1 0 0 LOW (invalid)!
  • 15. • when Q = 0 and Q’ = 1, the latch is said to be in the set state • R=LOW (and S=HIGH) S R Q Q' S R Q Q' 1 0 0 1 initial 1 1 0 1 (afer S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 invalid! 1 0 0 1
  • 16. • The inputs must go back to their normal conditions (S=1, R=1)before any changes occur S R Q Q' S R Q Q' 1 0 0 1 initial 1 1 0 1 (afer S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 invalid! 1 0 1 1
  • 17. • When Q = 0 and Q’ = 1, it is in the S R Q Q' S R Q Q' 1 0 0 1 initial 1 1 0 1 (afer S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 invalid! 0 1 1 0 reset state • R=LOW (and S=HIGH)
  • 18. • The inputs must go back to their normal conditions (S=1, R=1)before any changes occur S R Q Q' S R Q Q' 1 0 0 1 initial 1 1 0 1 (afer S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 invalid! 1 1 1 0
  • 19. If both inputs LOW a Q and Q' both S R Q Q' S R Q Q' 1 0 0 1 initial 1 1 0 1 (afer S=1, R=0) 0 1 1 0 1 1 1 0 (after S=0, R=1) 0 0 1 1 invalid! 0 1 0 1 LOW (invalid)!
  • 22. • Ensure that inputs S and R are never equal to 1 at the same time. • has only two inputs: D (data) and En (enable)
  • 23. When EN is HIGH, D=HIGH  latch is SET D=LOW  latch is RESET Hence when EN is HIGH, Q ‘follows’ the D (data) input. Characteristic table: EN D Q 1 0 0 Reset 1 1 1 Set 0 X Q No change

Editor's Notes

  1. The figure shows a theoretical view of how sequential circuits are made up from combinational logic and some storage elements Observations about sequential circuits from the diagram: The "state" of the sequential circuit is stored in the memory elements. There are a finite number of states the circuit can be in. The next state of the memory elements is a function of the current state and current inputs. Output of the circuit is a function of the current state and current inputs.
  2. A sequential logic circuit typically has some kind of memory element to hold the state of the circuit. The memory element is a device which can remember value indefinitely, or change value on command from its inputs. the whole idea is that in the memory, you’re going to be retaining certain states, The memory element also has a clock input which provides timing for changing states. To retain their state values, sequential circuits rely on feedback. Feedback in digital circuits occurs when an output is looped back to the input.
  3. A clock is an important part of a sequential circuit. It controls the timing of changes in a sequential circuit. State changes occur in sequential circuits only when the clock ticks. Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage. Circuits that change state on the rising edge, or falling edge of the clock pulse are called edge-triggered. Level-triggered circuits change state when the clock voltage reaches its highest or lowest level
  4. Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.
  5. Also known as active-HIGH input SR Latch The latch has two states When output Q = 1 and Q’ = 0, the latch is said to be in the set state . When Q = 0 and Q’ = 1, it is in the reset state . However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 (rather than be mutually complementary) occurs. If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1 is forbidden.
  6. The operation of the basic SR latch can be modified by providing an additional input signal that determines (controls) when the state of the latch can be changed by determining whether S and R (or S and R ) can affect the circuit. In the figure . It consists of the basic SR latch and two additional NAND gates. The control input En acts as an enable signal for the other two inputs.