4Sem VTU-HDL Programming Notes-Unit1-Introduction

1.
EVEN
SEMESTER
Professor,
E&C
Department,
PESIT
SC
Introduction
• HDL
and
B
rief
History
of
HDL
• Structure
of
HDL
Module
• Operators
&
Data
Types
• Types
of
Descriptions
• Simulation
and
Synthesis
• Brief
Comparison
of
Verilog
and
VHDL
Reference
Books:
• HDL
Programming
(VHDL
and
Verilog)-­‐
Nazeih
M.Botros-­‐
John
Weily
India
Pvt.
Ltd.
2008.
UNIT
1:
Introduction:
Why
HDL?
,
A
Brief
History
of
HDL,
Structure
of
HDL
Module,
Operators,
Data
types,
Types
of
Descriptions,
simulation
and
synthesis,
Brief
comparison
of
VHDL
and
Verilog
6
Hours
HDL
DESIGN-­‐4-­‐CLASS
NOTES
–
UNIT1
Shivananda
(Shivoo)
Koteshwar
P e o p l e s
E d u c a t i o n
S o c i e t y
S o u t h
C a m p u s
( w w w . p e s . e d u )
14

2. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Pre Requisites
Binary Number, Coding (Grey, BCD etc), Digital Logic Gates, Gate
Conversions, Boolean Algebra, SOP & POS, Canonical and Standard
Forms, Minterms and Maxterms, KMaps, Combinational Circuits (MUX,
Half Adder, Full Adder, Comparator, Multiplier) and Synchronous Circuits
(D FF, T FF, JK FF, Latch vs. FF, ModX Counter)
ASIC
FLOW
HDL and Brief History of HDL:
HDL - Hardware description language is used to design and document
electronic systems. It allows designers to design at various levels of
abstraction
Because it is both machine readable and human readable, it supports the
development, verification, synthesis, and testing of hardware designs; the
communication of hardware design data; and the maintenance, modification,
and procurement of hardware
Two languages
• VHDL: VHSIC (Very High Speed Integrated Circuit) HDL
• Verilog
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Koteshwar’s
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3. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Why HDL?
• Specifies the spec in a complete and unambiguous way
• HDL language spec is ‘soft’ compared to 'hard' form of schematics
• HDL can be simulated to uncover errors before the hardware is built
• Logic synthesis is possible. Tools are present which optimize the
design with reference to speed, frequency, power etc
• HDL is the best way to document a design
• Advantages:
o Abstraction, Speedy Creation, Verification
o Readability, Speedy Simulation, Interoperability
o Smart Portability, Easy Portability, Reliable Portability
Example to highlight the advantages of HDL coding
If we have to design an arbiter with these specifications (Spec)
• Two-agent arbiter.
• Active high asynchronous reset.
• Fixed priority, with agent 0 having priority over agent 1
• Grant will be asserted as long as request is asserted
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Koteshwar’s
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4. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
In the low level design, we follow these steps:
• Draw a state machine
• Make a truth table with state transitions for each flip-flop.
• Draw Karnaugh maps
• From K-maps get the optimized circuit.
• This method works just fine for small designs, but with large designs
this flow becomes complicated and error prone
It’s a lengthy and error prone! Using HDL coding, one can minimize the
effort
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5. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
History of VHDL:
• VHDL stands for Very High-Speed Integrated Circuit (VHSIC)
Hardware Description Language
• VHDL was developed in the early 1980s under the VHSIC program,
a program in which a number of high-tech companies were involved
in designing VHSIC chips for the U.S. Department of Defense
(DoD). Mainly IBM, TI and Intermetrics
o At this time each company used its own primitive HDL and
mostly were gate level tools
• The first publicly available standard was VHDL version 7.2 in 1985
• 1986: IEEE was tasked with globally standardizing the language
• 1987: IEEE standard 1076-1987 version was released
• 1993: VHDL was updated. IEEE 1076-1993. Most of the books have
this version
o Biggest enhancement of this version was that 7 additional logic
levels were introduced to existing 2 levels (logic 1 and logic 0)
History of Verilog:
Latest in Verilog World:
• 2001: A significantly revised version of Verilog was published IEEE
Std. 1364-2001. Top 5 enhancements were
o Verilog generate statement
o Multi-dimensional arrays
o Better Verilog file I/O
o Re-entrant tasks
o Better configuration control
• 2005: There was a further revision in 2005 but this only added a few
minor changes.
• There is also a draft standard for analog and mixed-signal extensions
to Verilog, Verilog-AMS
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6. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
• System Verilog:
o 2005: The advent of HDL such as OpenVera, and Verisity's e
language encouraged the development of Superlog by CoDesign Automation Inc. Co-Design Automation Inc was later
purchased by Synopsys. The foundations of Superlog and Vera
were donated to Accellera,
o Accellera developed a new standard, SystemVerilog, which
extends Verilog 2005. It came with many new features and
capabilities to aid design-verification and design-modeling
o 2009: SystemVerilog and Verilog language standards were
merged into SystemVerilog 2009 (IEEE Standard 1800-2009).
Design Flow Using Verilog
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7. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Structure of Verilog
Module is a basic building block in Verilog
• Verilog is case sensitive in contrast to VHDL
• The name of the module should start with an alphabetical letter and
can include special character underscore (_)
• Declaration of module starts with pre-defined word module followed
by a user selected name
• The names of inputs and outputs follow the same guidelines as the
module’s name. They are written inside parenthesis and are separated
by commas. The closing parenthesis is followed by a semicolon (line
separator)
• The order in which the input and output ports are written inside the
parenthesis is irrelevant.
• Carriage return does not indicate a new line; the semicolon does
• More than one input or output could be written on same line by
using a comma to separate each input
• Double slash signal a comment command. If the comment takes
more than one line, new double slashes can be used or pair (/* …*/)
can be used
• Leaving blank lines is allowed in the module. Spaces between two
words or at the beginning of the line is allowed
• Verilog ports can be one of the following 3 modes: in, out,
inout
• The module is terminated by the predefined word endmodule
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8. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Modules and Module Instantiation
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Koteshwar’s
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9. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
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Koteshwar’s
Notes
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10. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Operators
Functions:
Logical, Relational, Arithmetic, Shift & Rotate
There are 3 types of operators – unary, binary and ternary.
1. Unary operators – stand before the operand
b_cc = ~b; // ~ is a unary operator, b is the operand
2. Binary operators – stand between two operands
y = a||b; // || is a binary operator, a and b are
operands
3. Ternary operators – have two separate operators that separate three
operands
out=control?a:b; // ? Is a ternary operator, control, a
and b are operands
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Koteshwar’s
Notes
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11. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
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Koteshwar’s
Notes
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12. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Numbers and Strings:
• Sized numbers <size>`<base format><number>
5`b10111 // 5-bit binary number
16`hcdab // 16-bit hexadecimal number
3`d7
// 3-bit decimal number
• Unsized numbers
16549 // This is 32-bit decimal number by default
`o21 // This is 32-bit octal number
• 16`h536x // This is a 16-bit hexadecimal value with 4 least
significant bits unknown
• Negative numbers- Number with a minus sign before the size of a
constant number
-10`d9
•
Strings – Any characters enclosed by double quotes
“Verilog HDL Concepts”
“sum=a+b”
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Koteshwar’s
Notes
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13. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Single Bit and Multi Bit expression
In Verilog there are 4 values and 8 logic strengths: 4 driving, 3 capacitive,
and high impedance (no strength)
Note on High Impedance State:
• High impedance (also known as hi-Z, tri-stated, or floating) is the
united state of an output terminator which is not currently driven by
the circuit
• In digital circuits, it means that the signal is neither driven to a logical
high nor low level - hence "tri-stated". Such a signal can be seen as an
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Koteshwar’s
Notes
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14. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
open circuit (or "floating" wire) because connecting it to a low
impedance circuit will not affect that circuit; it will instead itself be
pulled to the same voltage as the actively driven output
• The combined input/output pins found on many ICs are actually tristate capable outputs, which have been internally connected to inputs.
This is the basis for bus-systems in computers, among many other
uses
• In digital circuits, a wire at high impedance may sometimes have a
voltage that is around, or even lower than, the threshold for a digital
0. This can cause people to mistakenly read a hi-Z wire as a digital 0.
To verify if a wire is at hi-Z, a large value pull-up resistor can be used
to try to pull the wire to high and low voltage levels
Truth Table with X and Z also as possible inputs
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Koteshwar’s
Notes
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15. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Data Types:
Verilog in contrast to VHDL does not have extensive data types.
Data types in Verilog are: nets, registers, vectors, integers, real,
parameters and arrays
Physical Data Types:
1. Wire (Nets)
2. Reg (Registers)
Abstract Data Types
1. Integer
2. Time
3. Real
4. Event
5. Parameter
6. Vector
Nets:
• Nets represent connections between hardware elements
• Nets are declared using the keyword wire
• By default, nets are one-bit values, unless they are declared as vectors
wire [7:0] idata; // 8-bit net idata
wire a,b,c; // Declare nets a, b and c for the following AND gate
Registers:
• Registers represent data storage elements
• Registers are declared using the keyword reg
reg Q, Q_BAR; // variables Q and Q_BAR can hold the value
reg [15:0] data_in; // 16-bit register variable data_in
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Notes
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16. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Vectors:
• Vectors are multiple bits
• A register or a net can be declared as a vector
• Vectors are declared by brackets
wire[3:0] a =4’b1010; //declares a net a which has 4 bits and its
initial value is 1010
reg[7:0] total = 8’d12; //declares a register total whose size is 8
bits and its value is decimal 12
Integers, Real and Parameters:
• Integers are declared by the predefined word integer
• Real (floating point) numbers are declared with the pre-defined word
real
• Parameters represent global constants. They are declared by the
predefined word parameter
parameter N=3;
input[N:0] X,Y;
output xgty, xlty, xeqy;
Wire[N:0] sum, Yb;
To change the size of the inputs X and Y and the size of the nets sum
and Yb to 8 bits, we now just have to change the value of N as:
parameter N=7
Arrays:
• Verilog does not have a predefined word for array (unlike VHDL)
• Verilog does not support multi dimensional arrays
• Registers and integers can be written as arrays
parameter N=4;
parameter M=3;
reg signed [M:0] carry [0:N];
reg [M:0] b [0:N];
integer sum[0:N];
The array carry has 5 elements and each element is 4 bits. The 4 bits
are in 2’s complement form i.e. if the value of certain element is 1001,
then it is equivalent to -7
The array b has 5 elements and each element is 4 bits
The array sum has 5 elements and each element is an integer type
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Koteshwar’s
Notes
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17. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Port Connection Rules:
There are two methods of making connections between signals specified in
the module instantiation and the ports in a module definition:
1. Connecting by ordered list
2. Connecting ports by name
• Connecting by Ordered List:
The signals in the module
instantiation appear in the same order as the ports in the port list of
module definition
• Connecting ports by name: In large designs where the number of
ports is great it may seem hard to use the ordered method of port
connection. Verilog provides the capability to connect external signals
to ports by the port names
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18. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Styles (Types) of Description
1.
2.
3.
4.
5.
6.
Behavioral Description
Structural Description
Switch-Level Description
Data-Flow Description
Mixed-Type Description
Mixed-Language Description
Behavioral Description
• Models the system as to how the outputs behave with the inputs
• The module includes the predefined word always
Structural Description
• Models the system as components or gates
• This description is identified by the presence of gates construct such
as and, or, or not in the module
Switch Level Description
• Switch Level description is the lowest level of description. The
system is described using switches or transistors
• Keywords nmos, pmos, cmos, tranif0, tran, tranif1
describe the system
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19. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Data Flow Description
• This describes how the system’s signals flow from the inputs to the
outputs
• Usually the description is done by writing the Boolean function of the
output
• The data flow statements are concurrent and their execution is
controlled by events
• Designer is aware of how data flows between hardware registers and
how data is processed in the design
• The module data flow description as defined above does not include
any of the key words that identify behavioral, structural or switch
level descriptions
Mixed Type Description
• This uses more than one type/style of the previously mentioned
descriptions
• Most of the moderate to large size systems are mixed
Mixed Language Description
• This a newly added tool for HDL descriptions
• The user now can write a module in one language and invoke or
import a construct (module) written in another language
• So basically can mix Verilog and VHDL
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20. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
SUMMARY
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Notes
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21. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Simulation and Synthesis
• Ultimate goal for HDL is to synthesize the system onto an electronic
chip
• Synthesis is a process of converting RTL to gate level netlist
• Before synthesis, we need to simulate and test it
• For testing, after we have written the logical code (RTL for the
design), we need to write a testbench to give inputs and trigger the
block so that we can monitor the output either in text format or in a
waveform format
• To test the design we must apply stimulus and check the results. The
stimulus block is commonly called a testbench
• There are two styles of Stimulus
Useful System Tasks:
System tasks – displaying on the screen, monitoring values of nets, stopping
or finishing simulations
Syntax:
$<keyword>
$display (“Verilog HDL”); // Display values of variables or
strings or expressions
$monitor (a,b,c,…..,y); // Continuously monitor the values
of variables or signals
$stop; // Puts the simulation in an interactive mode
$finish; // Terminates the simulation
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22. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
ARBITER EXAMPLE
Differences between Verilog and VHDL
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23. HDL
Design
(4th
Semester
VTU)
UNIT1
Notes
v1.0
Reserved Words in Verilog
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