1.
EVEN
SEMESTER
HDL
DESIGN-‐4-‐CLASS
NOTES
–
UNIT2
Shivananda
(Shivoo)
Koteshwar
Professor,
E&C
Department,
PESIT
SC
Data-‐Flow
Descriptions
• Structure
• Delay
Time
• Data
Type
–
Vectors
• Common
Programming
Errors
Reference
Books:
• HDL
Programming
(VHDL
and
Verilog)-‐
Nazeih
M.Botros-‐
John
Weily
India
Pvt.
Ltd.
2008.
UNIT
2:
Data-‐Flow
Descriptions:
Highlights
of
Data-‐Flow
Descriptions,
Structure
of
Data-‐Flow
Description,
Data
Type
–
Vectors.
6
Hours
P e o p l e s
E d u c a t i o n
S o c i e t y
S o u t h
C a m p u s
( w w w . p e s . e d u )
14
2. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
Data Flow - Structure
The keyword is “assign” in Verilog (and <= in VHDL). Steps to be
followed:
1. Understand the logic / Truth Table
2. Represent output as equations (Functions of inputs)
3. Use assign statement and represent the equation
Will this get synthesized or not?
Shivoo
Koteshwar’s
Notes
2
shivoo@pes.edu
3. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
• This will get synthesized because the wire s1,s2; will be implicitly
declared
Will this get synthesized or not?
• This will get synthesized because all these statements occur
simultaneously (concurrently) so the order does not matter
Will this get synthesized or not?
• This will not get synthesized because the simulator will not know
what is s1 and s2. Explicit declaration is required
Will these two give you the same netlist?
Shivoo
Koteshwar’s
Notes
3
shivoo@pes.edu
4. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
• Yes it will give the same netlist.
• The reason why we do the first one is to have a way to represent
internal delays
HALF ADDER:
Shivoo
Koteshwar’s
Notes
4
shivoo@pes.edu
5. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
Different Representation of the same Half Adder
NOTE: This will give same netlist as + in Verilog is deduced
internally as xor equation
Shivoo
Koteshwar’s
Notes
5
shivoo@pes.edu
6. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
Netlist of each of these representations:
Shivoo
Koteshwar’s
Notes
6
shivoo@pes.edu
18. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
Delay Time
• 2 types of assigning delays
1. Intra-Assignment Delay : variable = #t expression; Usually
used to model a gate delay
2. Delayed Assignment : #t variable = expression; Usually used
to model a delay. E.g. When an output of a multiplier is being
connected to one of the inputs of a logic gate
Shivoo
Koteshwar’s
Notes
18
shivoo@pes.edu
20. HDL
Design
(4th
Semester
VTU)
UNIT2
Notes
v1.0
Data Type - Vectors
• Vectors are multiple bits
• A register or a net can be declared as a vector
• Vectors are declared by brackets
wire[3:0] a =4’b1010; //declares a net a which has 4
bits and its initial value is 1010
reg[7:0] total = 8’d12; //declares a register total
whose size is 8 bits and its value is decimal 12
Shivoo
Koteshwar’s
Notes
20
shivoo@pes.edu