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4Sem VTU-HDL Programming Notes-Unit3-Behavioral Descriptions

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Dr. Shivananda Koteshwar
Dr. Shivananda Koteshwar

4Sem VTU-HDL Programming Notes-Unit3-Behavioral Descriptions

EducationTechnologyDesign
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  EVEN     SEMESTER                                                   Professor,  E&C  Department,  PESIT  SC           Behavioral  Descriptions     • Highlights     • Structure     • Sequential  Statements:  IF,  CASE,  FOR  LOOP,  WHILE  LOOP,  REPEAT,  FOREVER         Reference  Books:     • HDL  Programming  (VHDL  and  Verilog)-­‐  Nazeih  M.Botros-­‐  John  Weily  India  Pvt.  Ltd.     2008.         UNIT  3:     Behavioral  Descriptions:  Behavioral  Description  highlights,  structure  of  HDL  behavioral   Description,  The  VHDL  variable  –Assignment  Statement,  sequential  statements.   6  Hours       HDL  DESIGN-­‐4-­‐CLASS  NOTES  –  UNIT3   Shivananda  (Shivoo)  Koteshwar   P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )   14  
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   BEHAVIORAL - HIGHLIGHTS Models the system as to how the outputs behave with the inputs. The module includes the predefined word always or initial. • Behavioral description is a powerful tool to describe systems for which the digital logic structure are not known or are to generate • Examples of such systems are complex arithmetic units, computer control units and biological mechanisms that describe the physiological action of certain organs such as the kidney or heart • The behavioral description describes the system by showing how the outputs behave according to changes in the inputs • In this description, we do not need to know the logic diagram of the system; what must be known is how the output behaves in response to change in the input • The major behavioral description statements are always and initial • For VHDL, the statements inside the process are sequential and in Verilog all statements are concurrent The steps in behavioral style are: 1. Understand the logic / Truth Table 2. Use always statement and represent the logic using the code STRUCTURE OF THE BEHAVIORAL CODE • The code mainly consists of signal-assignment statements • The process is executed (activated) only if an event occurs on any element of the sensitive list; otherwise the process remains inactive. If the process has no sensitivity list, the process is executed continuously   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   n-bit Full Adder (Using Behavioral Style) SEQUENTIAL STATEMENT: IF   Shivoo  Koteshwar’s  Notes                                          3                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENT : IF ELSE IF   Shivoo  Koteshwar’s  Notes                                          4                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   D-Latch   Shivoo  Koteshwar’s  Notes                                          5                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENT : CASE • The case statement should include all possible conditions (Values) of the control expression • The statement default for Verilog ( when others for VHDL ) can be used to guarantee that all conditions are covered • begin and end are not needed if only a single statement is included for any test value • case resembles if, except that the correct condition in case is determined directly and not serially as in if statements   Shivoo  Koteshwar’s  Notes                                          6                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          7                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENTS : CASEX and CASEZ • casex ignores the “don’t care” values of the control expression • casez ignores the “high impedance” values of the control expression • casez allows for z values to be treated as don't cares, whereas casex allows for both z and x to be treated as don't cares. Only bit values other than the don't care bits are used in the comparison.   Shivoo  Koteshwar’s  Notes                                          8                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Question1: Convert from Dataflow to Conditional Dataflow and then to IF and CASE Solution:   Shivoo  Koteshwar’s  Notes                                          9                                                                                          shivoo@pes.edu        
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Question2: Write the stimulus block for the following   Shivoo  Koteshwar’s  Notes                                          10                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Edge Triggered JK Flip Flop   Shivoo  Koteshwar’s  Notes                                          11                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   3 Bit Binary Active High Synchronous Clear Counter   Shivoo  Koteshwar’s  Notes                                          12                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          13                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   3 Bit Binary Active High Asynchronous Clear Counter   Shivoo  Koteshwar’s  Notes                                          14                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Priority Encoder using CASEX   Shivoo  Koteshwar’s  Notes                                          15                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENTS: LOOP • LOOP is a sequential statement that appears inside always or initial block • Loop is used to repeat the execution of statements written inside its body. The number of repetitions is controlled by the range of the index parameter   Shivoo  Koteshwar’s  Notes                                          16                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   4 Bit Positive Edge Triggered Counter   Shivoo  Koteshwar’s  Notes                                          17                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          18                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          19                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   4 Bit Positive Edge Triggered Counter With Synchronous Hold   Shivoo  Koteshwar’s  Notes                                          20                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          21                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Factorial with WHILE LOOP   Shivoo  Koteshwar’s  Notes                                          22                                                                                    shivoo@pes.edu              
HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          23                                                                                    shivoo@pes.edu              

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4Sem VTU-HDL Programming Notes-Unit3-Behavioral Descriptions

  • 1.   EVEN     SEMESTER                                                   Professor,  E&C  Department,  PESIT  SC           Behavioral  Descriptions     • Highlights     • Structure     • Sequential  Statements:  IF,  CASE,  FOR  LOOP,  WHILE  LOOP,  REPEAT,  FOREVER         Reference  Books:     • HDL  Programming  (VHDL  and  Verilog)-­‐  Nazeih  M.Botros-­‐  John  Weily  India  Pvt.  Ltd.     2008.         UNIT  3:     Behavioral  Descriptions:  Behavioral  Description  highlights,  structure  of  HDL  behavioral   Description,  The  VHDL  variable  –Assignment  Statement,  sequential  statements.   6  Hours       HDL  DESIGN-­‐4-­‐CLASS  NOTES  –  UNIT3   Shivananda  (Shivoo)  Koteshwar   P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )   14  
  • 2. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   BEHAVIORAL - HIGHLIGHTS Models the system as to how the outputs behave with the inputs. The module includes the predefined word always or initial. • Behavioral description is a powerful tool to describe systems for which the digital logic structure are not known or are to generate • Examples of such systems are complex arithmetic units, computer control units and biological mechanisms that describe the physiological action of certain organs such as the kidney or heart • The behavioral description describes the system by showing how the outputs behave according to changes in the inputs • In this description, we do not need to know the logic diagram of the system; what must be known is how the output behaves in response to change in the input • The major behavioral description statements are always and initial • For VHDL, the statements inside the process are sequential and in Verilog all statements are concurrent The steps in behavioral style are: 1. Understand the logic / Truth Table 2. Use always statement and represent the logic using the code STRUCTURE OF THE BEHAVIORAL CODE • The code mainly consists of signal-assignment statements • The process is executed (activated) only if an event occurs on any element of the sensitive list; otherwise the process remains inactive. If the process has no sensitivity list, the process is executed continuously   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu        
  • 3. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   n-bit Full Adder (Using Behavioral Style) SEQUENTIAL STATEMENT: IF   Shivoo  Koteshwar’s  Notes                                          3                                                                                          shivoo@pes.edu        
  • 4. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENT : IF ELSE IF   Shivoo  Koteshwar’s  Notes                                          4                                                                                          shivoo@pes.edu        
  • 5. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   D-Latch   Shivoo  Koteshwar’s  Notes                                          5                                                                                          shivoo@pes.edu        
  • 6. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENT : CASE • The case statement should include all possible conditions (Values) of the control expression • The statement default for Verilog ( when others for VHDL ) can be used to guarantee that all conditions are covered • begin and end are not needed if only a single statement is included for any test value • case resembles if, except that the correct condition in case is determined directly and not serially as in if statements   Shivoo  Koteshwar’s  Notes                                          6                                                                                          shivoo@pes.edu        
  • 7. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          7                                                                                          shivoo@pes.edu        
  • 8. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENTS : CASEX and CASEZ • casex ignores the “don’t care” values of the control expression • casez ignores the “high impedance” values of the control expression • casez allows for z values to be treated as don't cares, whereas casex allows for both z and x to be treated as don't cares. Only bit values other than the don't care bits are used in the comparison.   Shivoo  Koteshwar’s  Notes                                          8                                                                                          shivoo@pes.edu        
  • 9. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Question1: Convert from Dataflow to Conditional Dataflow and then to IF and CASE Solution:   Shivoo  Koteshwar’s  Notes                                          9                                                                                          shivoo@pes.edu        
  • 10. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Question2: Write the stimulus block for the following   Shivoo  Koteshwar’s  Notes                                          10                                                                                    shivoo@pes.edu              
  • 11. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Edge Triggered JK Flip Flop   Shivoo  Koteshwar’s  Notes                                          11                                                                                    shivoo@pes.edu              
  • 12. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   3 Bit Binary Active High Synchronous Clear Counter   Shivoo  Koteshwar’s  Notes                                          12                                                                                    shivoo@pes.edu              
  • 13. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          13                                                                                    shivoo@pes.edu              
  • 14. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   3 Bit Binary Active High Asynchronous Clear Counter   Shivoo  Koteshwar’s  Notes                                          14                                                                                    shivoo@pes.edu              
  • 15. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Priority Encoder using CASEX   Shivoo  Koteshwar’s  Notes                                          15                                                                                    shivoo@pes.edu              
  • 16. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   SEQUENTIAL STATEMENTS: LOOP • LOOP is a sequential statement that appears inside always or initial block • Loop is used to repeat the execution of statements written inside its body. The number of repetitions is controlled by the range of the index parameter   Shivoo  Koteshwar’s  Notes                                          16                                                                                    shivoo@pes.edu              
  • 17. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   4 Bit Positive Edge Triggered Counter   Shivoo  Koteshwar’s  Notes                                          17                                                                                    shivoo@pes.edu              
  • 18. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          18                                                                                    shivoo@pes.edu              
  • 19. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          19                                                                                    shivoo@pes.edu              
  • 20. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   4 Bit Positive Edge Triggered Counter With Synchronous Hold   Shivoo  Koteshwar’s  Notes                                          20                                                                                    shivoo@pes.edu              
  • 21. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          21                                                                                    shivoo@pes.edu              
  • 22. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0   Factorial with WHILE LOOP   Shivoo  Koteshwar’s  Notes                                          22                                                                                    shivoo@pes.edu              
  • 23. HDL  Design  (4th  Semester  VTU)                                                                                                                UNIT3  Notes  v1.0     Shivoo  Koteshwar’s  Notes                                          23                                                                                    shivoo@pes.edu