Veriloggen.Stream: データフローからハードウェアを作る（2018年3月3日 高位合成友の会 第5回 @東京工業大学）

1. Veriloggen.Stream:
(@shtaxxx)
E-mail: takamaeda_at_ist.hokudai.ac.jp
2018 3 3
@

2. Veriloggen
n GitHub
l Veriloggen: https://github.com/PyHDI/veriloggen
l Pyverilog: https://github.com/PyHDI/Pyverilog
l IPgen: https://github.com/PyHDI/ipgen
n PIP Python
2
$ pip install veriloggen
$ pip install pyverilog
$ pip install ipgen
$ git clone https://github.com/PyHDI/veriloggen.git
$ git clone https://github.com/PyHDI/Pyverilog.git
$ git clone https://github.com/PyHDI/ipgen.git

3. Veriloggen:
Python RTL
3
Design Generator by Python
from veriloggen import *
m = Module('blinkled')
clk = m.Input('CLK')
led = m.Output('LED', 8)
count = m.Reg('count', 32)
m.Assign( led(count[31:24]) )
m.Always(Posedge(clk)(
count( count + 1 ) )
hdl = m.to_verilog()
print(hdl)
blinkled
CLK RST
LED count
assign
always
Veriloggen Object
module blinkled (
input CLK,
output [7:0] LED
);
reg [31:0] count;
assign LED = count[31:24];
always @(posedge CLK) begin
count <= count + 1;
end
endmodule
Verilog Source Code
module
input
CLK
input
RST
blinkled
Verilog AST
to_verilog()
Verilog
AST
Generator
Verilog
Code
Generator
Run on Python Interpreter
Verilog HDL
Python
Verilog HDL

4. Verilog
4
Module
Python
(m )Reg
"count <= 0"
"count==1023"
If
(m )Always
Module

5. Thread, Stream, and RTL together:
Veriloggen Mixed HW
5
Veriloggen.Core (RTL)
Thread
RAM
Thread
RAM
Stream
Stream
Computing
Unit
Thread
Python-to-FSM
Stream
Control
Thread Bus + DMA
(AXI4 Master/Slave)
AXI4 Interconnect DRAMCPU
RTL
Control
Intrinsic
RTL
RTL
Control DMA Control
DMA Burst Transfer

6. Thread: Python-to-FSM
LED
6
Module I/O
Verilog
( : CLK, RST, LED )
Thread
Python
I/O
Thread
FSM

7. RTL
FSM
7
FSM
LED
(th_blink FSM )

8. RTL
8
RTL
Seq ( )
RTL
( : )
Thread
Python
RTL

9. Intrinsic function/method:
RTL
9
FSM
send(fsm, value)
data <= value;
enable <= 1;
/* then */
enable <= 0;
wait(fsm)
if(ready) goto next;
RTL
→
Intrinsic function
RTL
Intrinsic function

10. Mutex
10
lock()
Mutex
unlock()
Mutex
Mutex
obj

11. DMA
11
I/F
RAM: RAM
AXIM: AXI4 IF
AXIS: AXI4 IF
Thread DMA
(Async )
dma_read: read
dma_write: write
Burst Read
Burst Write

12. : AXI-S
12
AXI4-lite
AXI4-lite

13. IP-XACT
13
HW
ipcore.to_ipcore() IP-XACT
IP

14. Verilog HDL
14
Module
m HDL

15. 15

16. Stream:
16
ram_a ram_b
ram_c
ACC+
source/sink
run/join
RAM

17. ) 1
17
ram_a ram_b
ram_c
ACC+
Mult Add

18. 18
3
:
0, 1, 2, 1, 2, 3, 2, 3, 4, …
:
0, 1, 2, 3, 4, …

19. Substream: Stream
19
MAC Stream

20. Thread/Stream DSL API
n
20

21. Stream
21
(OP)

22. n : Thread
l Icarus Verilog RTL
n HDL :
pytest
l GitHub + Travis CI
22

23. n Veriloggen: Python Mixed HW
l Veriloggen.Core: RTL
l Veriloggen.Thread: Python-to-FSM
l Veriloggen.Stream:
n "Veriloggen for DSL X"
l Veriloggen DSL
23
Veriloggen.Core (RTL)
Thread
RAM
Thread
RAM
Stream
Stream
Computing
Unit
Thread
Python-to-FSM
Stream
Control
Thread Bus + DMA
(AXI4 Master/Slave)
AXI4 Interconnect DRAMCPU
RTL
Control
Intrinsic
RTL
RTL
Control DMA Control
DMA Burst Transfer