RF Module Design - [Chapter 8] Phase-Locked Loops

RF Transceiver Module Design
Chapter 8
Frequency Synthesis and
Phase-Locked Loops
李健榮助理教授
Department of Electronic Engineering
National Taipei University of Technology

Outline
• Frequency Synthesis Techniques
• Frequency Synthesizers based on the Phase-Locked-Loop
• Loop Analysis and Stability
• Settling Time
• Loop Filters
• Noise Analysis
• PLL Architectures
• Summary
2/55 Department of Electronic Engineering, NTUT

Generic Transceiver Front End
• Local oscillator (LO) provides the carrier signal for both the
receive and transmit paths.
• If the LO output contains phase noise, both downconverted
and upconverted signals are corrupted.
BPF
LNA
Duplexer
Antenna
v
Frequency
Synthesizer LO
PA
BPF
Department of Electronic Engineering, NTUT3/55

Effect of Phase Noise in Receivers
f
0f
Wanted Signal
LO Output
Wanted Signal
Downconverted
Signal
f
Downconverted
Signals
ff
0f
Wanted Signal
LO Output Interferer
• Reciprocal mixing

Effect of Phase Noise in Transmitters
f
1f
Wanted Signal
Nearby Transmitter
2f
f
0f
Multi-carrier signal (or OFDM)
f
0f
• Receiver desensitization
• Orthogonality

• Meaning of frequency
• Meaning of frequency synthesis
Generation of a frequency or frequencies that are exact multiples of a reference
frequency. Usually the reference is very precise and the synthesized frequencies are
selectable over some range of whole-number multiples of a submultiple of .
Frequency Synthesis
out ref
n
f f
M
=
where n and M are integers, n varies from Nmin to Nmax, and M is constant.
( )v t
t
1T
1
1
f
( )V f
f
1f
reff

Transformation To and From Voltage or Current
A B1f
Frequency
Discriminator
∫
C D
d
dt
Voltage Controlled Oscillator
(VCO)
Phase Detector Phase Modulator
1 1v Af=
2 1f Bv=
1 1f dtφ = ∫ 2 1v Cφ= 2 2Dvφ =
3 2
d
f
dt
φ=
V/Hz Hz/V
V/rad or V/cycle rad/V or cycle/V

Demonstration of the Transfer Functions
rms rms rms rms rms
1 rad 2 V rad rad 1
1 V 2 V 2 V V 0.32 V
V cycle cycle 2 rad
AV
π π
 
= ⋅ = = = = 
 
RMS voltage at point A:
1 rms
MHz
0.32 V 1.5 0.48 MHz
V
f∆ = ⋅ = rms
2
0.32 V MHz
1 0.32 MHz
1 k mA
f∆ = ⋅ =
Ω
( ) rms
5 V
0.48 MHz-0.32 MHz 0.8 V
MHz
DV = ⋅ =
Phase Modulator
1 rad/V
Phase Detector
2 V/Cycle
220 MHz VCO
1.5 MHz/V
1 kΩ
200 MHz ICO
1 MHz/mA
100 MHz
signal
Low-pass Filter
50 MHz Cut-off
Frequency
Discriminator
5 V/MHz
A
B
D
Modulation voltage
(1 Vrms at 10 kHz)
C
and

• Frequency addition and subtraction:
Mathematical Operations on Frequency
( ) ( )cos 2RF RF RFv t A f tπ θ= +
( ) ( ) ( ) ( ) ( )cos 2 cos 2IF RF LO RF RF LO LOv t v t v t A f t B f tπ θ π θ= ⋅ = + × +
For the practical mixer with nonlinear operation:
IF RF LOf mf nf= +
( ) ( )cos 2LO LO LOv t B f tπ θ= +
( ) ( ) ( ) ( ){ }cos 2 cos 2
2
RF LO RF LO RF LO RF LO
AB
f f t f f tπ θ θ π θ θ= + + + + − + −      
( ) ( ){ } ( )cos2 cos2 for 0
2
RF LO RF LO RF LO
AB
f f t f f tπ π θ θ= + + − = =
( ) ( ), cosIF m nv t K m nα β= + 2 1f Bv= 2 LO LOf tβ π θ= +where and
or we can say the intermediate frequency is:
RF
LO
IF
Mixer

Frequency Synthesis Techniques
• Direct Analog Synthesis (DAS)
• Direct Digital Synthesis (DDS)
• Indirect Synthesis : Phase-Locked Loops (PLLs)
• Hybrid DDS/PLL

• Frequency generated by mixed frequencies
Direct Analog Synthesis (DAS) (I)
1f
2f
3f
2Nf −
1Nf −
Nf
outf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
out a bf mf nf= ±

• More stages are required for flexibly frequency planning.
Direct Analog Synthesis (DAS) (II)
1f
2f
3f
2Nf −
1Nf −
Nf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
filter1
filter2
filter3
filterN-2
filterN-1
filterN
outf
1f ′ 2f ′ 3f ′ 2Nf −
′ 1Nf −
′ Nf ′
( )out a b cf p mf nf qf= ± ±

Direct Digital Synthesis (DDS) (I)
ref cf f=
• Waveform construction is based on the lookup table (LUT)
and a digital to analog converter (DAC).
• Direct synthesis
• Generated frequency is lower than input frequency
Ref. Clk
Phase
Accumulator
Amplitude/Sin
Conv. Algorithm
DAC
Tuning
word
N
Digital Analog
2
o cN
M
f f= ⋅
M
Jump size
0000…0
1111…1
1111…0

Direct Digital Synthesis (DDS) (II)
• Hardware technique to reduce the spur level of a DDS
• Reduce bandwidth
1000 MHz
100−150 MHz 1100−1150 MHz 110−115 MHz
div-by-10
DDS Filter
Frequency
Divider
0f
outf
BW=50 MHz BW=15 MHz
reff

Hybrid DDS/DAS
1f ′ 2f ′ 3f ′ 2Nf −
′ 1Nf −
′ Nf ′
outf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
DDS
Frequency
Divider
reff
• Scheme to increase a DDS output bandwidth

• The main goal of the PLL is to sync the divided oscillator
frequency with the reference frequency .
Indirect Frequency Synthesis
( )outf N reff
( )out reff N f= out reff N f= ⋅
PFD: Phase frequency detector
LPF: Loop filter
VCO: Voltage controlled oscillator
/N: Divided-by-N frequency divider
Frequency divider
reff outf
/N
PFD LPF
VCO

Fractional-N Frequency Synthesis
• Lower division ratio N to reduce inband phase-noise gain
• Effectively produce a fractional division value
• Generally employee a delta-sigma modulator for division ratio
dithering
PFD LPF
Dual-modulus
Frequency Divider
reff outf
/N, (N+1)
FCW

Phase-Locked Loop Analysis

Feedback System
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )o i o i oV s V s V s H s G s G s V s V s G s H s= − = −  
( )
( )
( )
( )
( ) ( )1
o
i
V s G s
T s
V s G s H s
= =
+
Closed-loop
transfer function T(s)
G(s)H(s) is the
open-loop transfer function
( )iV s ( )oV s( )G s
( )H s
error
• Feedback loop:

Loop Analysis – Use Frequency as I/O
( ) ( )p
v
K
G s F s K
s
=
( )
1
H s
N
=
( )
( )
( )
( ) ( )
( )
( )
11
1
p
v
out
pref
v
K
F s Kf s G s s
Kf s G s H s
F s K
N s
= =
+
+
• Relation between input and output frequencies:
Phase differenceFrequency difference
Frequency Divider
( )reff s ( )outf s
1
s
pK
vK
1
N
( )outf s
N
PFD
LPF VCO
( )F s

• Relation between input and output phases:
Loop Analysis – Use Phase as I/O
( ) ( ) v
p
K
G s K F s
s
=
( )
1
H s
N
=
( )
( )
( )
( ) ( )
( )
( )
11 1
v
p
out
vref
p
K
K F ss G s s
Ks G s H s K F s
N s
φ
φ
= =
+ +
Frequency Divider
( )ref sφ ( )out sφpK ( )F s
vK
s
1
N
Phase difference Frequency to Phase
PFD
LPF VCO

Loop Transfer Functions
( )
( )
( )
( )
( )
( )
( ) ( )
0 0
0 01 1
p po
i p p
K F s K s K F s K G s
T s
K F s K Ns Ns K F s K G s H s
φ
φ
= = = =
+ + +
T(s) : closed-loop PLL transfer function
G(s) : forward-path transfer function
F(s) : loop filter transfer function
Kp: phase detector gain
K0/s: VCO transfer function
( ) ( )1 0G s H s+ = ( ) ( ) 1 0 dB@ 180G s H s = − = ∠ −
H(s) : feedback-path transfer function
G(s)H(s) : open-loop transfer function
or
• A PLL is unstable when
The condition of unity open loop gain and a phase angle of 180 degrees must be
avoided.

PLL Response w/o a Loop Filter (I)
( ) 0 0
0 01
F
p LPFo
Fi p LPF
K
K K K s NT s N N
KK K K Ns ss
N
φ ω
φ ω
= = = =
+ ++
( ) LPFF s K=
0ω
logω
dB
0
FK
N
ω ω= =
20log N
3 dB
0ω
• Closed-loop transfer function:
Without the loop filter, the feedback loop is equivalent to a DC gain of N plus a
low-pass filter (in dB) with cutoff at .
3 dB cutoff frequency is KF/N = KpKLPFK0/N .
With

• The simplest PLL is called a type-I loop because the open-loop
gain has one pole at DC (pure integration). It is also a first-
order loop because the open-loop gain has one significant pole:
• The open loop gain has a slope of −6 dB/octave or −20
dB/decade for all frequencies.
• The phase angle is always −90 degrees at all frequencies.
Hence with no low-pass filter, the PLL is always stable. But the
main drawback is that designers loose control over the loop.
PLL Response w/o a Loop Filter (II)
( ) ( )
( )p vK F s K
G s H s
Ns
=

• The function of the LPF is to filter out any high frequency
harmonics in the loop.
• Adding a LPF also affects the loop response including
parameters such as the loop time response, bandwidth, and the
damping factor.
• If we add a low-pass filter with a pole located at , the loop
will be still type-I, but it will become a second-order loop.
Single Pole Loop Filter
( )
( )1
LPF
p
K
F s
s ω
=
+
( ) ( )
1 1
p LPF v F
p p
K K K K
N NG s H s
s s
s s
ω ω
= =
   
+ +      
   
pω

Bode Plot of Open-Loop Transfer Function
( ) ( )
( )
1
G s
G s H s
N
= = ( )G s N= (forward-loop gain )
log mω
( ) ( )m mG Hω ω
6 dB/oct−
1020log FK
N
0 dB
Lω
pω1mω =
90−
135−
180−
( )mG ω∠
12 dB/oct−
Phase margin
• Where the curves cross, the open-loop gain equals unity.

• Prototype 2nd-order equation:
• Natural frequency:
• Damping ratio:
Natural Frequency and Damping Ratio
( )
( )
( ) ( )
( )
( )
0
0
1
1 1 1 1
1
F
ppo F
Fi p
F
p
p
K
ss
K F s K sG s NK
T s
KG s H s K F s K Ns sNs K
sNs
ωφ
φ
ω
ω
 
+ 
 = = = = =
+ +  + + +    + 
 
0
F p
n p
K
N
ω
ω ω ω= =
0
1 1 1
2 2 2
p p
p
n F
N
K
ω ω
ς ω
ω ω
= = =
It is geometric mean of the loop bandwidth in the absence of a filter and the filter
corner frequency.
2
2 2 2 2
2 2 2
p F p F n
p F n n n n
p
K K
N
K s s s s
s s
N
ω ω ω
ω ςω ω ςω ω
ω
= = =
+ + + +
+ + Characteristics equation

• The poles of the closed-loop function:
• As long as damping ratio is greater than one, the poles are real
and a tangential plot of closed loop gain looks like:
Closed-Loop Gain for Large Damping
20log N
6 dB/oct−
12 dB/oct−
log mω
( )out
ref
f
s
f
2 2
0 2 1 1 1ω ω ς ς = − −
 
2
1 1 1
2
pω
ω ς = + −
 
The characteristics are similar to the case with no loop filter, except for the
increasing rate of attenuation in fout/fref beyond approximately the filter corner
frequency .
2
1p n ns ςω ω ς= − ± −
0ω
pω
pω

• As decreases toward , the damping ratio decreases and
the phase shift at increases. Correspondingly, the transient
response of the loop becomes less damped (more ringing) and
the response peaks near .
Close-Loop Responses
0
F p
n p
K
N
ω
ω ω ω= =
0
1 1 1
2 2 2
p p
p
n F
N
K
ω ω
ς ω
ω ω
= = =
pω 0ω
0ω
nω
m nω ω
0.25 0.5 1 2 4
12 dB
6 dB
0 dB
−6 dB
−12 dB
−18 dB
−24 dB
0.1ς =
0.3
0.5
0.7
1
( )
1 out
ref
f
N f
ω
0mω ω
0.1ς =12 dB
6 dB
0 dB
−6 dB
−12 dB
−18 dB
−24 dB
−30 dB
0.25 0.5 1 2 4
( )
1 out
ref
f
N f
ω
0.3
2
0.5 0.7 1
Tangent for no filter

Relative Stability – Phase Margin
• Right figure shows the phase margin
(relative stability) as a function of the
damping factor. More highly damped
loops are safer, in that more parameter
variation is allowable before instability
occurs.
log mω
( ) ( )m mG Hω ω
6 dB/oct−
1020log FK
N
0 dB
Lω
pω1mω =
90−
135−
180−
( )mG ω∠
12 dB/oct−
Phase margin
• With a single-pole low-pass filter, the
loop is inherently stable, sine −180o
phase shift cannot be attained for any
finite frequency. (not always true practically)
Department of Electronic Engineering, NTUT
ς
0.2 0.3 0.5 0.7 1.0 2.00.1
10
20
30
40
50
60
70
80
0
90
1
4
1 1
90 tan 1 1
2 4
PM
ς
−
 
= − + −  
 
PhaseMargin(degrees)
30/55

Transient Response
0t = t
oldf
newf
Synthesizer
output frequency
A
B
C
D
Overshot
Ringing
• Lower damping ratio brings
a higher percent overshoot
can cause the loop to go out
of lock. (more unstable)
• Narrower bandwidth with
smaller damping ratio and
longer settling time.
1N
2N
1 refN f
2 refN f
( )2 1N N>
e
1
2
1 ref
N
f
N
 
− 
 
t
reff outf( )G s
1 N
e
31/55

Settling Time
( )
( )0
02.3
log
f
T
f Tω
∆
∆
≃
oldf
newf
( )0f∆
0t = t T=
( )f T∆
3 -1
1 MHz/cycle 10 secFK = =
10 kHzreff =
11 MHz 10 MHzoutf = →
Find the settling time for the output frequency of 10.1 MHz is attained:
6
0
10
1000
1000
FK
N
ω = = =
0
2.3 1
log 2.3 ms
0.1
T
ω
=≃
• Settling time:
The frequency error changes one decade approximately each 2.3 time constant, i.e.,
• Example (no filter):
32/55

• The addition of a pole in the transfer function causes the
slope to drop at a rate of −6 dB/oct whereas the addition of a
zero has the opposite effect.
• The open loop transfer function is:
• The closed-loop transfer function is:
A Pole-Zero Filter
( )
( )
( )
1
1
z
p
s
F s
s
ω
ω
+
=
+
( ) ( )
( ) ( )
( )
1
1
p v zp v
p
K K sK F s K
G s H s
Ns Ns s
ω
ω
+  = =
 + 
pω
zω
6 dB/oct−
12 dB/oct−
log mωzωpω
6 dB/oct−
( )
( )
( )
0
01
po
i p
K F s K s
T s
K F s K Ns
θ
θ
= =
+

Open-Loop Gain with a Pole-Zero LPF (I)
( )
( )
2
1
1
p F
z
p F p F
p
z
K
s
NT s N
K K
s s
N N
ω
ω
ω ω
ω
ω
+
=
 
+ + + 
 
0
F
n p p
K
N
ω ω ω ω= =
1
2
p n
n z
ω ω
ς
ω ω
 
= + 
 
6 dB/oct−
12 dB/oct−
log mω
zωpω
6 dB/oct−
( )2
2 2
1
2
z
n
n n
s
N
s s
ω
ω
ςω ω
+
=
+ +
• Given the pole frequency location, a zero can be placed after
the so as to avoid the magnitude from crossing the unity gain
axis at a slope of −12 dB/oct, and therefore avoiding instability.
To determine the closed loop response, simply plot T(s):
34/55

• From the results:
Selecting the pole frequency sets the natural frequency and subsequently the
loop bandwidth.
Selecting the zero (based on the pole location in the open loop gain response)
determines the desired percentage overshoot.
• Therefore, a pole-zero filter allows the designer to select the
loop bandwidth and the damping factor independently and still
achieve stability.
Open-Loop Gain with a Pole-Zero LPF (II)
0
F
n p p
K
N
ω ω ω ω= =
1
2
p n
n z
ω ω
ς
ω ω
 
= + 
 

• The simplest PLL is the type-I loop because the open-loop gain
has one pole at DC (pure integration). It is also a first-order
loop because the open-loop gain has one significant pole.
Type and Order of the Loop
( )
( )
( ) ( )
( )
( )1
G s N s
T s
G s H s D s
= =
+
( ) 1
1 0
n n
n nN s a s a s a−
−= + + +⋯
( ) 1
1 0
m m
m mD s b s b s b−
−= + + +⋯
Order = m (m roots)
Type = n (n roots at DC)
( )ref sφ ( )out sφpK ( )F s
vK
s
1
N
PFD
LPF VCO

• First order, type I (no loop filter)
First-order Type I
Lω
log mω0 dB
G
6 dB/oct.−
1R
iv ov
2R
2
1 2
o
LPF
i
v R
G
v R R
= =
+
A−
3R
iv
4R
ov′
A → ∞
4
3
o
LPF
i
v R
G
v R
′
′− = = −

• Second order, type I (lag-and-lead filter)
Second-order Type I (I)
1R
iv ov
2R
1C
A−
3R
iv
5R
ov
2C
4R
Lω
log mω0 dB
G
12 dB/oct.−
6 dB/oct.−
zωpω
1
1
z
LPF
p
s
G
s
ω
ω
+
=
+
2 1
1
z
R C
ω =
( )1 2 1
1
p
R R C
ω =
+
1
1
z
LPF
p
s
G
s
ω
ω
+
′
′− =
+
′
4 5
2
4 5
1
z
R R
C
R R
ω′ =
+
5 2
1
p
R C
ω′ =

• Second order, type I (lag filter)
Second-order Type I (II)
Lω
log mω0 dB
G
6 dB/oct.−
pω
12 dB/oct.−
2
1 2
1
1
LPF
p
R
G
sR R
ω
−
=
+ +
4
3
1
1
LPF
p
R
G
sR
ω
′− = −
+
′
1 1 2
1 1 1
p
C R R
ω
 
= + 
  4 2
1
p
R C
ω′ =
1R
iv ov
2R 1C
A−
3R 4R
ov′
2C
A → ∞
iv
39/55

• Second order, type II (integrator and lead filter)
Second-order Type II
Lω
log mω0 dB
G
12 dB/oct.−
6 dB/oct.−
zω
1 1
1
1 z
LPF
s
G
R C s
ω
+
− = −
2
1
z
R C
ω =
A−
1R
iv
2R
ov
C
A → ∞
40/55

• Third order, type II (integrator plus lead-lag filter)
Third-order Type II
Lω
log mω0 dB
G
12 dB/oct.−
pω
12 dB/oct.−
6 dB/oct.−
zω
1 1
1
1
1
z
LPF
p
s
G
R C s
s
ω
ω
+
− = −
 
+  
 
3 3
1
1
1
z
LPF
p
s
G
R C s
s
ω
ω
+
′
′− = −
 
+  ′ 
( )2 1 2
1
z
R C C
ω =
+ 2 2
1
p
R C
ω =
4 3
1
z
R C
ω′ =
5 4
1
p
R C
ω′ =
A−
1R
iv
2R
ov
2C
1C
A → ∞
A−
3R
iv
4R
ov′
3C
5R
4CA → ∞
41/55

PLL Phase Noise Model
Frequency Divider
Xtal
,ref nφ
outφ
1
N
PFD LPF
,pfd nV ,op nV ,vco nφ
,div nφ
VCO
+ ++ +
+
( )
( ) ( )( ) ( ), , , , , ,out n pfd n op n ref n div n e vco n
d
T s
V V T s H s
K
φ φ φ φ= + + + +
( )
( )
( ) ( )1
G s
T s
G s H s
=
+
( )
( ) ( )
1
1
eH s
G s H s
=
+
( )
( )
( ) ( ) ( )
for
for1
c
c
NG s
T s
G sG s H s
ω ω
ω ω
<<
= ≈ 
>>+ 
( )
( ) ( )
( )
for1
for1
1
c
e
c
N
G sH s
G s H s
ω ω
ω ω

<<
= ≈ 
>>+ 

where
Very useful results
42/55

Responses of Noise Transfer Functions
cω
log mω
( )
( ) ( )1
G s
G s H s+
N
( )G s
Transfer function multiplying
all sources except VCO
cω
log mω
( ) ( )
1
1 G s H s+
1
( ) ( )
1
G s H s
Transfer function for VCO
cω log mω
20log N
( )dB
0
Other sources dominate
inband noise
VCO dominates
outband noise
43/55

Typical VCO and PLL Noise Performance
( )L f∆
(dBc/Hz)
VCO
PLL
( )log f∆1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
−120
−90
−60
−30 dB/dec
−20 dB/dec
44/55

Phase-Locked Loop Architectures
• Integer-N PLL
• Offset PLL
• Fractional-N PLL
• DDS offset PLL
• Dual loop PLL
• Multi-loop PLL
45/55

• Extend bandwidth with different
• Avoid LO pulling
Offset PLL
out ref offsetf N f f= ⋅ +
offsetf
PFD LPF
Frequency Divider
reff outf
/N
offsetf ?
46/55

Offset PLL − Dual-Loop PLL (I)
PFD LPF
Frequency Divider
reff outf
/N
PFD LPF
Frequency Divider
offsetf
/M
47/55

Offset PLL − Dual-Loop PLL (II)
PFD LPF
Frequency Divider
1reff outf
/N
PFD LPF
Frequency Divider
offsetf
/M
2reff

Offset PLL − Hybrid DDS/PLL
PFD LPF
Frequency Divider
reff outf
/N
DDS
offsetf

Multi-Loop PLL
PFD LPF
Frequency Divider
reff outf
/N
1offsetf
PFD LPF
/M
PFD LPF
/P
2offsetf
3offsetf
50/55

• Effectively produce a fractional division value
• Generally employee a delta-sigma modulator for division ratio
dithering
Fractional-N Frequency Synthesis
PFD LPF
Dual-modulus
Frequency Divider
reff outf
/N, (N+1)
FCW
51/55

• DDS acts a reference source or phase/frequency modulator
• A variable reference frequency source can drive a fractional
frequency output.
DDS-Driven Fractional-N Synthesizer
PFD LPF
Frequency Divider
reff outf
/N
Hybrid DDS/PLL
FCW
DDS
52/55

DDS-feedback Fractional-N Synthesizer
2
out ref offsetn
M
f f f= ⋅ +
PFD LPF
DDS as a
Frequency Divider
reff outf
DDS
FCW
Hybrid DDS/PLL
• DDS acts a frequency divider
• DDS output frequency:
53/55

Comparison of Frequency Synthesizers
DDS
Single-Loop
PLL
Multi-Loop
PLL
DDS/DAS
DDS Offset
PLL
DDS Driven
PLL
BW
(output)
Narrow
< 100MHz
Broad
> 1GHz
Broad
> 1GHz
Broad
> DDS
Broad
(carefully
design)
Broad
Resolution
Extremely
Fine
< 0.02 Hz
Very Course
> 250kHz
(typical)
Medium
> 1kHz
(typical)
Extremely
Fine
< 0.01 Hz
Extremely
Fine
< 0.01 Hz
Extremely
Fine
< 1Hz
Switching
Time
Very Fast
< 100 ns
Fast
< 100us
(typical)
Very Slow
> 1ms
(typical)
Very Fast
< 1us
(limited by
RF switch)
Fast
< 100us
(typical)
Trade-off vs
close-in
spurious
tones
Spurious
Noise
< 75dBc
(limited by
DAC)
Very Good
Good
(carefully
design)
Minimum
Close-in
Spurious
Minimum
Close-in
Spurious
Excellent
over Broad
Bandwidth
Phase
Noise
Better than
clock
reference
Very Good Very Good Very Good Very Good Good
Circuitry Simple Simple Very Complex Moderate Moderate Moderate

Summary
• In this chapter, the basic idea of the phase-locked loops
derived from the feedback system was introduced. One may
put attention on that the PLL is processing the phase (or
frequency) by transforming the phase error into voltage or
current signals.
• The PLL transient response and the phase noise were also
presented in this chapter. We can simply conclude that, as loop
bandwidth increases, the locking time is going faster and the
VCO inband phase noise can be suppressed with more
attenuation while the other components contribute more noise
within the loop bandwidth.

RF Module Design - [Chapter 8] Phase-Locked Loops

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RF Module Design - [Chapter 8] Phase-Locked Loops