Design Compiler already has the set target_library my_lib.db command. Why is it necessary to also use the set link_library "* my_lib.db" command? Can you explain the difference?

1. Difference Between target library and link library Variables in
Design Compiler
Ahmed Abdelazeem
February 4, 2024
Description
This documentation discusses the distinction between the target library and link library variables
in the context of Design Compiler.
Question
What is the Difference Between the target library and link library Variables?
Design Compiler already has the set target library my lib.db command. Why is it necessary to
also use the set link library "* my lib.db" command? Can you explain the difference?
Answer
The target library variable specifies the library that Design Compiler uses to select cells for optimiza-
tion and mapping. It is typically set only to the standard cell library. You can specify multiple libraries
when synthesis includes multithreshold libraries (such as lvt.db and hvt.db).
The link library variable specifies every library that has cells referenced by the netlist. The tool uses
the libraries specified in the link library variable for resolving references (linking). The link library
variable can include memory libraries (RAM, ROM, or any macro) in addition to the standard cell
library.
Listing 1: Example link library command
set s y n t h e t i c l i b r a r y ” dw foundation.sldb ”
set t a r g e t l i b r a r y ” gates.db ”
set l i n k l i b r a r y ”* $ s y n t h e t i c l i b r a r y $ t a r g e t l i b r a r y io.db rams.db”
The asterisk (*) stands for Design Compiler memory, meaning all designs that have already been
loaded into Design Compiler. The synthetic library variable specifies the DesignWare library, which
contains more complex cells.
The input design files for Design Compiler are often written using a hardware description language
(HDL) such as Verilog or VHDL. Design Compiler uses technology libraries, synthetic or DesignWare
libraries during the synthesis process.
During the synthesis process, Design Compiler translates the HDL description to components extracted
from the generic technology (GTECH) library and DesignWare library. The GTECH library consists of
basic logic gates and flip-flops. The DesignWare library contains more complex cells such as adders and
comparators. Both the GTECH and DesignWare libraries are technology independent, that is, they are
not mapped to a specific technology library.
After translating the HDL description to gates, Design Compiler optimizes and maps the design to
a specific technology library, known as the target library. The process is constraint-driven. Constraints
are the designer’s specification of timing and environmental restrictions under which synthesis is to be
performed.
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2. Design Compiler uses the link library to resolve references. For a design to be complete, it must connect
to all the library components and designs it references. This process is called linking the design or
resolving references.
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