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UC Berkeley has partnered with Intel and Microsoft to build the world’s #1 research lab to “accelerate developments in parallel computing and advance the powerful benefits of multi-core processing to mainstream consumer and business computers.” inst.eecs.berkeley.edu/~cs61c   UCB CS61C : Machine Structures   Lecture 40 –  Parallelism in Processor Design   2008-05-05 Lecturer SOE Dan Garcia parlab.eecs.berkeley.edu How parallel is your processor?
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Background: Threads CPU Time Thread 0 Thread 1 Thread 2
Background: Multithreading ,[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Background: Multicore
Cell Processor (heart of the PS3) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],Peer Instruction ABC 0:  FFF 1:  FF T 2:  F T F 3:  F TT 4:  T FF 5:  T F T 6:  TT F 7:  TTT
Peer Instruction Answer ,[object Object],[object Object],[object Object],ABC 0:  FFF 1:  FF T 2:  F T F 3:  F TT 4:  T FF 5:  T F T 6:  TT F 7:  TTT ,[object Object],[object Object],[object Object]
Conventional Wisdom (CW) in Computer Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Uniprocessor Performance (SPECint) ,[object Object],[object Object],[object Object],From Hennessy and Patterson,  Computer Architecture: A Quantitative Approach , 4th edition, Sept. 15, 2006    Sea change in chip design: multiple “cores” or processors per chip 3X
Sea Change in Chip Design ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Parallelism again? What’s different this time? ,[object Object],[object Object],[object Object],[object Object]
Need a New Approach ,[object Object],[object Object],[object Object],[object Object],[object Object]
7 Questions for Parallelism ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],(Inspired by a view of the  Golden Gate Bridge from Berkeley)
Hardware Tower: What are problems? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
HW Solution: Small is Beautiful ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Number of Cores/Socket ,[object Object],[object Object],[object Object],[object Object],[object Object]
Measuring Success: What are the problems? ,[object Object],[object Object],[object Object],[object Object],[object Object]
Build Academic Manycore from FPGAs  ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
And in Conclusion… ,[object Object],[object Object],[object Object],[object Object],[object Object]
Bonus slides ,[object Object],[object Object],Bonus
Why is  Manycore  Good for  Research ?  SMP Cluster Simulate RAMP Scalability (1k CPUs) C A A A Cost (1k CPUs) F  ($40M) C ($2-3M) A+  ($0M)  A  ($0.1-0.2M)  Cost of ownership A D A A Power/Space (kilowatts, racks) D  (120 kw, 12 racks) D  (120 kw, 12 racks) A+  (.1 kw, 0.1 racks)  A  (1.5 kw,  0.3 racks)  Community D A A A Observability D C A+ A+ Reproducibility B D A+ A+ Reconfigurability D C A+ A+ Credibility A+ A+ F B+/A- Perform. (clock) A  (2 GHz) A  (3 GHz) F  (0 GHz) C (0.1 GHz) GPA C B- B A-
Multiprocessing Watering Hole ,[object Object],[object Object],[object Object],Parallel file system Flight Data Recorder Transactional Memory Fault insertion to check dependability Data center in a box Internet in a box Dataflow language/computer Security enhancements Router design Compile to FPGA Parallel languages RAMP 128-bit Floating Point Libraries
Reasons for Optimism towards Parallel Revolution this time ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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Parallelism Processor Design

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  • 2. UC Berkeley has partnered with Intel and Microsoft to build the world’s #1 research lab to “accelerate developments in parallel computing and advance the powerful benefits of multi-core processing to mainstream consumer and business computers.” inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 40 – Parallelism in Processor Design 2008-05-05 Lecturer SOE Dan Garcia parlab.eecs.berkeley.edu How parallel is your processor?
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  • 22. Why is Manycore Good for Research ? SMP Cluster Simulate RAMP Scalability (1k CPUs) C A A A Cost (1k CPUs) F ($40M) C ($2-3M) A+ ($0M) A ($0.1-0.2M) Cost of ownership A D A A Power/Space (kilowatts, racks) D (120 kw, 12 racks) D (120 kw, 12 racks) A+ (.1 kw, 0.1 racks) A (1.5 kw, 0.3 racks) Community D A A A Observability D C A+ A+ Reproducibility B D A+ A+ Reconfigurability D C A+ A+ Credibility A+ A+ F B+/A- Perform. (clock) A (2 GHz) A (3 GHz) F (0 GHz) C (0.1 GHz) GPA C B- B A-
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Editor's Notes

  1. Autotuners is fine. I had a slightly longer list I was working on before seeing Krste's mail. PHiPAC: Dense linear algebra (Krste, Jim, Jeff Bilmes and others at UCB) PHiPAC = Portable High Performance Ansi C FFTW: Fastest Fourier Transforms in the West (from Matteo Frigo and Steve Johnson at MIT; Matteo is now at IBM) Atlas: Dense linear algebra now the "standard" for many BLAS implementations; used in Matlab, for example. (Jack Dongarra, Clint Whaley et al) Sparsity: Sparse linear algebra (Eun-Jin Im and Kathy at UCB) Spiral: DSP algorithms including FFTs and other transforms (Markus Pueschel, José M. F. Moura et al) OSKI: Sparse linear algebra (Rich Vuduc, Jim and Kathy, From the Bebop project at UCB) In addition there are groups at Rice, USC, UIUC, Cornell, UT Austin, UCB (Titanium), LLNL and others working on compilers that include an auto-tuning (Search-based) optimization phase. Both the Bebop group and the Atlas group have done work on automatic tuning of collective communication routines for supercomputers/clusters, but this is ongoing. I'll send a slide with an autotuning example later. Kathy
  2. Autotuners is fine. I had a slightly longer list I was working on before seeing Krste's mail. PHiPAC: Dense linear algebra (Krste, Jim, Jeff Bilmes and others at UCB) PHiPAC = Portable High Performance Ansi C FFTW: Fastest Fourier Transforms in the West (from Matteo Frigo and Steve Johnson at MIT; Matteo is now at IBM) Atlas: Dense linear algebra now the "standard" for many BLAS implementations; used in Matlab, for example. (Jack Dongarra, Clint Whaley et al) Sparsity: Sparse linear algebra (Eun-Jin Im and Kathy at UCB) Spiral: DSP algorithms including FFTs and other transforms (Markus Pueschel, José M. F. Moura et al) OSKI: Sparse linear algebra (Rich Vuduc, Jim and Kathy, From the Bebop project at UCB) In addition there are groups at Rice, USC, UIUC, Cornell, UT Austin, UCB (Titanium), LLNL and others working on compilers that include an auto-tuning (Search-based) optimization phase. Both the Bebop group and the Atlas group have done work on automatic tuning of collective communication routines for supercomputers/clusters, but this is ongoing. I'll send a slide with an autotuning example later. Kathy