Document

1. DESIGN AND IMPLEMENTATION OF LOW COST
VLSI ARCHITECTURE FOR MULTISTANDARD
INVERESE TRANSFORM
SUPERVISOR
Mrs.C.Jeyalakshmi.M.E,Ph.d;
Associate Professor,
Dept. of Electronics And
Communication Engineering,
Trichy Engineering college
TEAM 23
M.Atchaya.
E.Harini.
E.Obeth Saral Mary.
jothishanthi8@gmail.com

2. PROBLEM DESCRIPTION
The intercommunications between the video devices using
 iThe intercommunications between the video devices using
different standards are difficult.
 Integrating Multistandard encoding and decoding circuits into
a single chip will increase area and power.
n a single chip will increase area and power.

3. OBJECTIVE
 Multistandard codecs achieve both high performance and low
cost.
 The circuit share is an efficient method for resource reduction
such as area and power.
 Similar coding tools from different standards may be integrated
in a single chip through circuit share.
 So that the area of the integrated multistandard chip is much
smaller than the total areas of these single standard chips.

4. MODULES
MODULE 1 - DECODER PART OF MPEG4
MODULE 2 - DECODER PART OF VC-1
MODULE 3 - INTEGRATION OF MPEG4 &VC-1
MODULE 4 - 1D IDCT MULTISTANDARD
ARCHITECTURE

5. FUNCTIONAL BLOCK DIAGRAM
Input
Buffer
Parallel to
serial
convertor
Multistandard
IDCT
FS AS
Clk Ctl
unit
Carry Look
Ahead Adder
Serial to
Parallel
Convertor
O/P
Buffer
Display
unit
Area,
Power

6. MPEG-4??????
MPEG-4 - key enabling technology .
Supports IPMP
Efficient compression of images and video
Content-based scalability of textures, images and video

7. CIRCUIT ARCHITECTURE FOR
MPEG 2/4 8 POINT IDCT

8. T8 = P8,l T4 0 P8,r
IDCT matrix
0 V4
 The implementation of T4 needs 16 multiplications and 12
additions.
It can be further decomposed using recursion property

9. FACTOR SHARE CIRCUIT

10. FACTOR SHARE
NNow the multiplier-less transform SBF is preferred.
The element 473 can be factorized as 2^8 − 2^5 −
2^3 + 2^0
The SBFs can be shared in the multiplier-less
implementation of the integer IDCT.
ow the multiplier-less transform SBF is preferred.

11. VC-1?????????
VC-1 is a video codec specification to ensure content
delivery and interoperability
 High image quality with excellent compression
efficiency.
VC-1 is capable of delivering high-definition video at
bit rates as low as 6 to 8 Mbps

12. ADDER SHARE CIRCUIT

13. ADDERS-Consumption of circuit resources than operators.
AS –employed to share the adders.
For M IDCTs M-1 adders are saved.

14. INTEGRATION ARCHITECTUTE

15. a(x)
a(x)
fg(x)
fg(x)
bcde(x)
bcde(x)
bcde(x)
bcde(x)
Adder
Tree
xx5x4
x0
x2
x6x
x1
x3
x5
11-D
IDCT
o/p
data
-D /p
at
V4
Inverse
i/p data
X0
X4
X2
x2
x
6
x
X
X3
X1
x0
X7
X5
X6
Inverse
Quanti-
zation i/p
data
T4
V4

16. FRAMEWORK
Input data(X0-X7)
T4Xe V4X0
a(x) fg(x) bcde(x)
x0,x4 x2,x6 x1,x3,x5,x7

17. MPEG-4

18. DESIGN SUMMARY

19. POWER SUMMARY

20. POWER VS PARAMETERS

21. VC-1

22. DESIGN SUMMARY

23. POWER SUMMARY

24. POWER VS PARAMETERS

25. INTEGRATION

26. DESIGN SUMMARY

27. POWER SUMMARY

28. POWER SUMMARY

29. 1-D IDCT MULTISTANDARD
ARCHITECTURE

30. DESIGN SUMMARY

31. POWER SUMMARY

32. POWER VS PARAMETERS

33. EXISTING AND PROPOSED
ARCHITECTURE
ARCHITECTURE GATE COUNTS DECODING
CAPABILITY
WORKING
FREQUENCY
TECHNOLOGY
Lee’s 19.1k 1920x1080@22HZ 136MHZ 0.18
Ngo’s 21.5k 4096x2304@30HZ 176MHZ 0.35
PROPOSED 18K 1920X1080@60HZ 100MHZ 0.13

34. ADVANTAGES
HThroughput is high.
 Efficient latency.
 High decoding capability is achieved in small IDCT
architecture.
h dAPPLICATION a
Widely applied in video.
Widely applied in digital tv,video
conference,mobile video.

35. FUTURE ENHANCEMENT
Future development of the project could be made by replacing
Carry look ahead adder by Sklansky and Brentkung adder.
Gate count is decreased below 18KHZ .
 Java code is also applicable .

36. CONCLUSION
Thus the real-time decoding of 1920X1080@60Hz high
definition video can be supported.
The performance analysis can be carried out using the
parameters area and power.

37. Thank You

38. Queries