This document discusses the implementation and testing of a power-line communication system for connecting digital appliances to a home network. The system uses ultra-low-cost power-line communication (ULP) over the power cord between appliances and outlets. A communication node called a "smart adapter" located at the outlet bridges ULP to home networking protocols. The document describes the network structure, ULP physical layer details, and a microcontroller peripheral implementation of ULP functions to minimize appliance costs and software impacts. Testing of a prototype peripheral showed reliable communication below a bit error rate of 10-6.

1. Implementation and Test of a Power-Line based
Communication System for Electrical Appliances
Networking
Andrea Ricci∗ , Valerio Aisa§ , Ilaria De Munari∗ , Valerio Cascio§ and Paolo Ciampolini∗
∗ Dept.of Information Engineering, University of Parma, Parma, Italy.
Email: andrea.ricci@nemo.unipr.it, {ilaria.demunari, paolo.ciampolini}@unipr.it
§ Wrap S.p.A., Fabriano (AN), Italy. Email: {Valerio.Aisa, valerio.cascio}@indesitcompany.com
Abstract— This paper discuss the development of a low-cost,
narrow-band transmission system, aimed at connecting digital
Communication node micro-
appliances to a home network. The proposed approach is based
( PLC , ZigBee , WiFi , ...) controller
on powerline communication (ULP: Ultra Low-cost Powerline),
AFE CPU
carried out on the power-supply wire between the appliance ULP
micro-
and the outlet. Through ULP, appliance can communicate with controller
AFE peripheral
a transceiver node located at the outlet, the “smart adapter”,
which, in turn, can flexibly route messages toward external
control devices (e.g., for diagnostic purposes) or, more generally, Smart
Adapter
toward a home control network. At the appliance side, such Low-Cost
an approach allows for connectivity at extremely low costs, at Power-Line Communication
Digital Appliance
the same time keeping independent of the actual home control
network protocol (since different configurations of the smart Home Network
adapter take care of it). To make practical their implementation
on a variety of digital appliances, ULP communication functions Fig. 1. Network structure.
have been implemented in a dedicated hardware device, conceived
as a dedicated peripheral for a general-purpose microcontroller.
In this work, details on the peripheral architecture and its
implementation are given. A prototype of the peripheral has leaves the field open to new smart solutions. A new approach
been developed, based on a FPGA board directly connected to has been proposed in [5] and [6], based on a novel network
the microprocessor bus. This closely emulates the perspective structure, which allows for each digital appliance to esta-
microcontroller architecture, and allowed for extensive testing
blish an ultra low-cost half-duplex power-line communication
of the device under realistic operating conditions. Complete
characterization of ULP protocol has been carried out, estimating (called ULP: Ultra Low-cost Powerline) on its power-supply
BER figures well below 10−6 . cord. A general-purpose communication node (called a ”smart
adapter”, SA) located, for instance, at the outlet then acts as a
I. I NTRODUCTION bridge between the ULP communication and the actual home-
Microelectronic technology fostered the pervasive diffusion networking protocols. Using this method, i) communication
of digital controllers. Modern household appliances embed costs at the appliance side are kept at a minimum and,
microcontrollers to manage all tasks; digital cores are used, ii) communication with the specific home-networking protocol
for example, to control electric actuators and to manage sensor are delegated to the the smart adapter, so that the internal
signals. Furthermore, digital domain computation allows for appliance architecture does not care about standard protocols
the deployment of innovative features. Among these new at all, and the same appliance may communicate with different
characteristics, connectivity is expected to become a standard networks just by exploiting the proper SA. Moreover, since
in the next future. This will enable for innovative services appliance additional costs due to ULP are negligible, ULP
like preventive maintenance, remote control and smart power features can be implemented on every produced item, regard-
management. Networking will improve functionality, safety, less of its actual need of networking. As a side-effect, this
reliability and performance of appliances. provide an effective and inexpensive way for factory testing
To this purpose, the adoption of several communication as well.
protocols, either wired or wireless, had been proposed (Kon- In a previous paper [5] a preliminary FPGA-based imple-
nex [2], LonTalk [1], Ethernet [3], ZigBee [4]). However, mentation for ULP peripheral supporting upstream commu-
high-priced communication nodes, typical of these solutions, nication was introduced; in this paper, an improved solution
prevent most of them from being effectively exploited for will be discussed: some basics of the approach have been
low-cost “white goods” networking. Moreover, the absence revised, aiming at lowering EMC disturbances, and at adding
of universal agreement on a recognized home-networking some functionalities. In the following, the novel architecture is
standard, makes the protocol selection a difficult task and described, aiming at implementing the ULP algorithms into a

2. 300
SA over the power distribution network has been drastically
200
100 reduced, at the same time making it possible to attain a higher
throughput (200 bit/s).
m
0
VS
-100 power supply
-200
Figure 2(a) reports an example of controlled glitches
perturbations m
-300 (VS ), generated by zener diodes connected in series with
0 5 10 15 20 appliance power supply. The same figure shows the smart
adapter transmission section, where a digital device controls
zc 1
2
0
0 5 10 15 20 to digital current flowing through the diodes by means of a couple of
peripheral MOSFETs and a relay. At the appliance side (see Fig. 1(b)),
zc2
2
0
an inexpensive analog front-end (AFE), made by a band-pass
0
L1off
5 10 15 20
t [ms] filter and two Schmitt-triggers, couples the power section to
L1Vj
L2off L2Vj
the digital circuitry.
In Fig. 2, examples are given of digital signals zc1 and zc2 ,
a) provided by the AFE to the digital section. zc1 allows for
synchronization, by triggering at the sinewave zero crossing,
smart adapter transmitter appliance receiver
ZL
eq whereas zc2 tracks data encoded glitches.
Z ULP Perturbations are generated twice within a power supply
uC period, in order to account for the actual nature (i.e., inductive
m with
Vs Vs BPF ULP or capacitive) of the appliance load. In fact, a perturbation
interface
control logic generated during the first quarter of power-supply period is
not properly revealed when inductive reactance are plugged
b) to the power-line. On the other hand, second-quarter glitches
are missed if capacitive loads are connected. To cope with
Fig. 2. ULP upstream communication: signals, smart adapter transmission this, the first half of supply voltage period is divided into two
section and appliance receiver. transmission intervals, and the j th packet of M bit
Dj = {dM j , dM j+1 , ..., dM j+M −1 } , (1)
dedicated microcontreller peripheral. Within this perspective,
is transmitted twice (i.e., once within each interval). Data are
the hardware emulation of such a peripheral is discussed and
encoded by modulating the perturbation positions, with respect
physical implementation issue (chip area and power consump-
to the zero-crossing of supply voltage waveform. Modulation
tion) are analyzed. Performances of the peripheral have been
expressions read:
experimentally evaluated, under realistic operating conditions.
g(Dj )
L1 = L1 f + L1 j = L1 f +
j of V of 2M
LVmax
s(Dj ) (2)
II. N ETWORK S TRUCTURE AND ULP PHYSICAL LAYER L2 = L2 f + L2 j = L2 f +
j of V of 2M
LVmax
Figure 1 describes the network structure. Each digital where g is the Gray encoding function, s is an encoding
appliance establish a half-duplex communication with an function described later on, L1 f and L2 f are time offsets,
of of
external device, here called “smart adapter”, located at the and LV max is the shift range. In figure, for instance,
outlet. Transmission is carried out on the power supply cable, parameters are the following: L1 f = 1 ms, L2 f = 7 ms,
of of
according to an ultra low-cost power-line communication LVmax = 2 ms, with the AC supply voltage period T set at 20
protocol described below. The smart adapter, placed between ms.
the appliance power-supply plug and the outlet, acts as a bridge Measurements demonstrate that it is possible to transmit
towards the home network. At the one end, the smart adapter at least one nibble (M = 4) at a time without exceeding
manages ULP communications with the appliance, while, at noise limits set by regional standardization committees (e.g.,
the opposite end, it embeds specific network controllers which CENELEC in Europe) and preserving the proper functionality
allows for interfacing to wired (e.g. broadband PLC, ethernet, of the appliance.
etc.) as well as wireless (e.g. Wi-Fi, ZigBee, etc.) networks. As already discussed above, information data have to be
duplicated and encoded into both the transmission intervals,
A. Smart Adapter to Digital appliance communication in order to ensure that at least one pulse will trigger the
In [5], basics of the power modulation scheme exploited by receiver. When both glitches reach the receiver, noise can
ULP were introduced; in particular, upstream communication affect the positions of received pulses, due to appliance load
(i.e., from the smart adapter to digital appliance) relies on variations within a period. Hence, error correction should be
intentional and precise perturbations of the power supply performed: as described in Fig. 3, the coding function s allows
waveform. With respect to the previous implementation, here a for maximize the distance among pulse nominal values within
more efficient scheme is accounted for: by introducing lower- the receiving space. At the appliance side, measured intervals
amplitude glitches on the waveform, the noise injected by the (represented by circles in figure) are rounded to the nearest

3. k
15 cycle, the mean power PT reads:
14 nominal
13 (k+1)T
couples N −1
12 1 1 T T
11 of pulses k
PT = P dt ∼
= P kT + +i . (5)
10 T N i=0
2N N
9 kT
8 received
The resulting scheme is very robust and reliable and can be
7 couples
L1V
6 implemented at practically no additional costs.
5
of pulses
4 III. M ICROCONTROLLER PERIPHERAL IMPLEMENTATION
3 decision
2
As already discussed above, transceiver tasks at the ap-
1 intervals pliance side are kept as simple as possible, in order to lower
0 the overhead induced by communication. Software implemen-
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2 tation of these tasks on the appliance native microcontroller is
LV therefore relatively inexpensive; nevertheless, letting a small
hardware device take care of them would minimize the im-
Fig. 3. Receiving space partitioning for M = 4. pact on both the appliance software and physical resources.
Additional hardware costs would be negligible as well, if the
ULP hardware controller were integrated as a peripheral into
nominal values (represented by up triangles) and decoded as the existing microcontroller architecture. Aiming at this, to
follows: investigate the practicality of such an approach, we made
reference to the Renesas H8 microcontroller family, widely
ˆ
Dj = min d ¯ ¯
L1 j , L2 j , g D , s D , (3) adopted for white goods applications. We have developed a
¯ V V
D∈D prototypal implementation of the ULP peripheral, and tested
it on the Renesas development system based on the E6000
here, d is the Euclidean distance and D is the set of 2M packets emulation board ([7]).
of M -bit. Figure 4 describes system setup: the microcontroller emu-
Again, the main concern here is to keep the digital control lator allows for access to the internal bus signals so that
at the appliance side as simple as possible: as already stressed an additional board, embedding a FPGA device, can directly
above, the AFE, in order to provide the ULP logic with square communicate with the microcontroller CPU core. ULP digital
waves zc1 and zc2 , just includes a couple of Schmitt triggers peripheral has been implemented within the programmable
and a fist-order band-pass filter. Extracting delays between zc1 logic. Connection of the emulated microcontroller to the
rising edge and zc2 falling edges is almost trivial: if such appliance target board is performed by means of a flat cable the
intervals are larger than L1 f or L2 f , a message coming from
of of header of which features a standard chip footprint connector.
the smart adapter is recognized and decoded by measuring The ULP peripheral architecture is detailed in Figure 5, and
L1 or L2 respectively. Decoding tasks just require elementary
j j can be divided into six functional blocks: a register interface, a
binary counters. Besides, equation 3 is implemented by means module for signal conditioning, transmitter, receiver, line info
of a simple look-up table. and low-power control block. Peripheral operations are per-
formed using 1 MHz system clock, derived from the appliance
B. Digital Appliance to Smart Adapter communication microcontroller. Communication between ULP peripheral and
CPU is performed using a register interface. The register set
Downstream communication, instead, is based on the modu- includes five 8-bit registers: control register (PMCR), status
lation of instantaneous power consumption [5]. Data can be
easily encoded in the supply current by activating a small
triac which, in turn, drives an inexpensive load (ZULP ). Let’s appliance
assume a set of binary data dk is to be transmitted; the power supply cord
expression of appliance current, IDA , is therefore: microcontroller
header cable ULP peripheral address &
with chip footprint (FPGA device) data bus
VM 2π
IDA = sin t dk pT (t − kT ) , (4)
ZU LP T
k AFE
where pT is the port function, T is the AC period, and ZU LP
is the impedence of modulation load.
At the smart adapter, data coming from the electrical appliance microcontroller
target board expansion board emulator
are decoded by measuring the mean power required by the
appliance during each k-th cycle of the supply voltage. If N
samples of the instantaneous power P (t) are acquired per Fig. 4. Microcontroller development system.

4. MICROCONTROLLER ARCHITECTURE
Line info block monitors the power supply. It evaluates
amplitude and frequency of the supply voltage, by using the
same time interval estimation techniques exploited by the
CPU receiver section. Supply voltage amplitude is evaluated during
periods not involved in data communication (negative half of
address bus & data bus
power supply waveform); this allows the supply-voltage meter
to share the same hardware resources related to receiver block.
Power SPI The amplitude is thus extracted from eq. (6), by measuring
Register Interface Controller the time interval between Schmitt-triggers’ outputs; assuming
PWM the signal is sampled n clock periods after a zero-crossing
Transmitter Receiver Line Info
reference time (i.e., first trigger’s output), the amplitude is
Signal conditioning TIMER x related to the second trigger’s threshold voltage (Vth ) by the
ULP Peripheral ( FPGA Altera FLEX 10K ) following relationship:
Standard Peripheral
RX ( zc 1 , zc 2 ), TX ( triac control) Vth Vth
VM = 2π = 2π . (6)
Power Supply Cord
sin T nTclk sin 104 n
Analog Front-End
To abtain precise results, a calibrating step is required for
this section of ULP peripheral too: to deal with tolerance of
Fig. 5. ULP peripheral architecture. Schmitt-trigger threshold (Vth ), the voltage meter has to be
configured once by using a known reference voltage source.
The last block control the peripheral power consumption,
register (PMSR), data register (PMDR), voltage-measure re- enabling various modes of operation. These includes a normal
gister (PMVMR) and clock-generation register (PMCGR). All active mode and different power-down modes, to keep power
of the registers share access to common interface with the mi- requirement as low as possible. in which power consumption is
crocontroller, based on address- and data-buses and read/write significantly reduced. Power reduction is achieved exploiting
mode signals. The peripheral status is signalled through a set hierarchical clock-gating. Power-management modes include:
of five interrupt flags, allowing for microcontroller supervision • Active mode: since transmission, reception and power-
and to cope with exceptions (such as overrun errors and black- supply monitoring happens at separate time slots within
out detection). the power supply period, are separated time functions, the
The macrocell takes care of signal conditioning: square waves relative hardware modules are enabled one at a time by
zc1 and zc2 are routed through noise suppressors before being the power control block. provides one module at a time
latched internally. Their edges are used to generate trigger with clock signal, reducing total power consumption.
signals for subsequent processing blocks. • Subactive mode: only the essential tasks are enabled
The receiver module operates in two distinct modes: an initial
calibrating phase, and the actual running mode. Calibration
is necessary to deal with tolerances of low-cost AFE compo- 2125
L 1 [us] P L l L 2 = 0,6636
nents: to this purpose, the receiver is first trained by means of 2000
-2 time slots
error correction bounds
a fixed sequence of known data, from which the actual mean -2.5
0,3
nominal couple of pulses
1875 f L2
value of the offsets L1 f and L2 f are extracted. When only
of of 0,2
1750 -3
one offset can be computed, his value is exploited for either P L 2 = 0,3364
1625
transmission intervals. In the operating phase, interruptions -3.5
0,1
length are measured through binary counters. If only one pulse 1500
fL L -4
l 2 0,0
per period triggers the receiver, data is decoded according to 1375
7500 7625 7750 7875 8000 8125 8250 10^
7800 7825 7850 7875 7900 7925 7950
L 2 [us]
equations 2, accounting for the calibrated value L1 f or L2 f .
of of
a) L 2 [us]
b)
2500
When a couple of glitches is received, operations described in L 1 [us] P L l L 2 = 0,0382
-3.2
equation 3 are performed instead. 0,3
2375 -3.4
Decoded nibbles are used by the RRC (Receiver Register fLl P L l = 0,9618 2250 -3.6
Control) block to build data bytes, to be stored into data 0,2 2125 -3.8
register. Contemporarily, receiver state flags are set in the 0,1
2000 -4
status register. The receiver block also detects power supply 1875 -4.2
failures, by testing if voltage interruptions length exceedes the 0,0
fL L
l 2
2050 2075 2100 2125 2150 2175 2200 1750
7000 7125 7250 7375 7500 7625 7750 10^
AC period value. If this occurs, a proper interrupt flag is raised. L 1 [us]
L 2 [us]
c) d)
The transmitter section generates the mask signal m(t) (which
controls power modulation triac TU LP ), by means of a shift Fig. 6. Examples of distribution functions: a), b) report fL1 L2 and fL2
register, triggered by the zero-crossing signal zc1 and loaded, while transmitting Dj = 0x5; c), d) measured distribution functions with
eight bit at a time, from data register PMDR. Dj = 0x8.

5. by this mode: power control block halts logic not
strictly necessary to communication (e.g., power-supply
monitor).
• Stand-by mode: the stand-by mode is activated if a
single pulse received
SLEEP instruction is executed by the microcontroller 1 1
20 Lamp
E{L j }- L 0j Appliance Input Filter
core. The peripheral clock is turned down and no 15 Washing Machine P2
[us] Washing Machine P3
operation is carried out; register contents are preserved 10 Washing Machine P5 a)
and I/O ports are placed in high-impedance state. 5
0
IV. E XPERIMENTAL R ESULTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
In order to validate the communication principle and σ{L1j } 10
investigate the microcontroller peripheral performance, an [u s]
extensive set of experimental measurements was carried out 5
b)
in a thorough field test. To this purpose, a set of static and
time-variable appliance loads were connected to the power- 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
line, to simulate the actual operating environment. First, 2 2
20
E{L j }- L 0j 15
measurements were performed using a barely resistive load, [us ]
10
5
represented by a 25 W lamp, always connected to the power 0 c)
-5
supply cord at the appliance side. The same device was also -10
-15
exploited to perform downstream communication, modulating -20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
the current flowing over the power supply cord, as described
15
in Section II-B. σ{L2j }
Next, capacitive and time-dependent inductive loads were [u s] 10
taken into account, by connecting an actual washing-machine d)
5
to the network. Capacitive behavior was obtained exploiting
appliance power-supply filters, whereas an inductive load 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
was given by the washing-machine electrical engine. Time- couple of pulses received
dependent behavior was induced by performing several differ- 1 1 80
E{L j }- L 0j
ent washing cycles. Data collected during measurements were 60
[us] e)
processed to extract statistics and BER performances. Figure 40
6 reports examples of distribution functions evaluated at the 20
0
appliance side, whith the running washing-machine loading 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
the network. Plots (a) and (b) were obtained for a given 30
σ{L1j }
transmitted nibble, i.e., Dj is equal to 0x5. Probability of 25
[u s] 20
both glitches reaching the receiver within the default time slot 15 f)
is estimated to be P = 0.5769. In 0.0867% of transmission 10
5
events the pulses are outside default bounds, although they 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
still falls within the error correction area defined by encoding 30
functions g and s. During the remaining transmissions (P = 2 2
E{L j }- L 0j 25
20
15
0.3364), only second quarter pulses trigger the receiver, and [us ] 10
5 g)
always fall within the right time slot. Plots (c) and (d) illustrate 0
-5
-10
the response for a different transmission (Dj equal to 0x8). -15
-20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 7 shows the summary of statistical data collected
during communication under different load conditions. Plots
σ{L2j } 10
(a) and (b) reports statistics of pulse position when only one [u s]
glitch is received during fist transmission interval. Plot (a) 5
h)
shows the mean difference between measured and nominal
pulses position as a function of data transmitted (Dj ) and 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
load states (bar graph shade). The related standard deviation Dj
distribution is shown in (b). Plots (c) and (d) refer to the
mean and standard deviation of pulse position, respectively, Fig. 7. Mean and standard deviation of perturbation positions collected
evaluated when glitches were received only during the second during communication with a washer, having different load states.
transmission interval.
The same distributions, shown in Figure 7(e)-(h) for both
intervals, are eventually given, when both pulses trigger the
receiver. As already highlighted, a couple of pulses within

6. TABLE I
S YNTHESIS RESULTS USING UMC 0.18µm STANDARD CELL LIBRARY
actual test implementation in the real device is foreseen in the
next months.
Hierarchy Cell Area [µm2 ] Pdyn [µW ] Pleakage [nW ]
VI. C ONCLUSION
ULP interface 28008 138.98
active mode: 97.72 In this paper a communication system for electrical appli-
subactive mode: 87.28 ances networking is discussed. Its main goal is that of allowing
standby mode: 26.19
register interface 7051 68.32 34.95
for networking digital household appliances, without adding
signals conditioning 567 1.46 2.10 significant costs and staying independent of the actual home-
receiver 13424 18.40 71.01 networking protocol. This is achieved by transferring higher-
transmitter 2603 3.27 11.84 level communication tasks to an external “smart adapter” de-
line info 3135 4.62 14.56
power control 1228 1.65 4.52
vice, which may manage different protocols and serve different
appliances. Local communication is achieved by exploiting a
low bit-rate, ultra low-cost power-line communication (ULP)
the supply voltage period may imply a higher noise impact protocol between the appliance and the smart adapter.
with respect to a single trigger event. This is reflected by Formal basics of the ULP protocol have been illustrated,
the higher mean difference and standard deviation reported and improvements over the first prototype version have
in (e)-(h), which give reason of the introduction of the error- been discussed. Better performances, with respect to [5], are
correction technique described in Section II-A. obtained: the transmission reliability was improved and the
Results illustrated so far validate the proposed solution injected noise was reduced. Perspectively, higher bit rates are
for upstream communication. Furthermore, experimental data also achievable.
suggest that the same communication principle can be applied Experiments were made, aimed at evaluating costs and
using higher M value, allowing for throughput improvement. performance of a hardware implementation of a ULP con-
After fully validating the circuit functionality, an experimental troller: the architecture has been conceived as a microcon-
estimate of the Bit Error Rate associated to the ULP protocol troller dedicated peripheral, and a prototype was mapped
was also carried out. A BER figure well below than 10−6 was on a FPGA board. The board, in turn, was connected to a
evaluated, which is more than appropriate for the application microcontroller development system, directly accessing the
at hand. microntroller buses and allowing for realistic test. The ULP-
enabled microcontroller was then exploited for the protocol
V. UMC 0.18µm S TANDARD -C ELL I MPLEMENTATION validation, by performing an extensive set of measures. A test
To probe further the feasibility and practicality of the environment, including actual appliances, was set up to this
hardware implementation of the ULP peripheral, a VLSI purpose. Fully satisfactory results were obtained, both in terms
implementation was also carried out, by referring to a com- of performance and implementation issues, paving the way
mercial technology, similar to the fabrication technology of the toward the actual chip fabrication. ULP capabilities would then
target microcontroller. The design was fully synthesized in a come at negligible costs, providing an effective and flexible
standard-cell fashion, by using Synopsys Design Analyzer [8]. way for low-cost networking of digital appliances.
With reference to the UMC 0.18 µm commercial technology,
ACKNOWLEDGMENT
the implementation of the ULP controller required a total cell
area of about 0.028 mm2 , corresponding to 2894 equivalent The authors would like to thank T.Watanabe, G. Clark and
logic gates. The estimated dynamic power consumption of M. Mazzoni from Renesas Corporation for their support to
the ULP interface equals 97.72 µW , at 1.8 V power supply. this work.
Stand-by power consumption is much lower, in the range of R EFERENCES
29.19 µW .
[1] Echelon Corporation, LonTalk Protocol Specification, version 3.0. 1994.
Table I gives more detailed results of the preliminary synthesis [2] Konnex Association, KNX Standard. 2001.
process; in order to estimate the relative weight of different [3] Institute of Electrical and Electronics Engineers, Inc., IEEE Std 802.3.
subsystems, each block has also been independently synthe- IEEE Computer Society, 2002.
[4] Institute of Electrical and Electronics Engineers, Inc., IEEE Std 802.15.4.
sized and simulated. This allow for appreciating contributions IEEE Computer Society, 2004.
of different subsystems to the power and area budget. With [5] A. Ricci, V. Aisa, V. Cascio, G. Matrella and P. Ciampolini, “Connecting
respect to the preliminary implementation results given in electrical appliances to a Home Network using low-cost Power-line
Communication”, in Proc. 2005 International Symposium on Power-Line
[5], the improved functionality introduced here requires more Communications, pp. 300-304.
chip area than first implementation. On the other hand, imple- [6] V. Aisa, P. Falcioni and P. Pracchi, “Connecting white goods to a home
mentation of the power control module allows for consistent network at a very low cost”. International Appliance Manufacturing,
2004.
reduction in power-consumption. The overall power and area [7] Renesas Technology Corp., H8/300H Series E6000 Emulator, User’s
figures estimated so far are well below reasonable limits for the Manual, rev. 2.0, version 12.12.2000.
actual implementation within the industrial microcontroller; [8] Synopsys, Design Analyzer Reference Manual, version 05.2002.