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VLSI Design and Layout Practice Lect5 – Stick Diagram & Scalable Design Rules Danny Wen-Yaw Chung Institute of Electronic Engineering Chung-Yuan Christian University Sept. 2008
IC Layout Concept and Examples ,[object Object],[object Object],[object Object],Ref: http://140.135.9.56/XMS/
 
 
A. Basic Concept ,[object Object],Legend: contact metal 2 metal 1 poly ndiff pdiff VDD in VSS out ■
A. Basic Concept ,[object Object],[object Object]
B. Notations of the stick diagram
Stick Diagram ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
Stick Diagram ,[object Object],[object Object],[object Object],[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
Stick Diagram ,[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
Stick Diagram ,[object Object],[object Object],[object Object]
Conclusion ,[object Object],[object Object],[object Object]
CMOS Inverter Stick Diagrams ,[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
[object Object],CMOS Inverter Stick Diagrams V DD in VSS out
CMOS Transmission Gate The transmission gate Circuit schematic Stick diagram
CMOS Stick Diagrams NAND/NOR
[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1 CMOS Stick Diagrams NAND
< Exercise 1 > To draw the following circuitry by using a stick diagram
< Exercise 2 > To draw the stick diagram and the schematic for the following layout
CMOS Stick Diagrams [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1 NOR
CMOS Inverter Mask Layout Min. spacing and line width consideration
[object Object],[object Object],[object Object],[object Object],[object Object],Lambda-based Design Rules
Lambda based design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of  can be used to produce a new mask set. All device mask dimensions are based on multiples of  , e.g., polysilicon minimum width = 2  . Minimum metal to metal spacing = 3  Lambda-based Design Rules 6  2  6   3  3 
Active Contact and Surround Rule
Potential Problem - Misalignment
Potential Problem – Short between Source and Drain
Degree of anisotropy A = 1 – r lat /r vert Where r  respective etch rates Physical Limitations
Design Rule (0) ,[object Object],[object Object]
The purpose of design rules ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Design Rules(1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
Design Rules(2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
Terminology & Definition ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],Terminology & Definition
Terminology & Definition ,[object Object],[object Object]
Conventional Layer Definition
SCMOS Design Rules ,[object Object]
SCMOS Design Rules
SCMOS Design Rules
SCMOS Design Rules [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
MOSIS Layout Design Rules ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
III. Layout Verification ,[object Object],[object Object],[object Object],[object Object],[object Object]
Layout Verification ,[object Object],[object Object],[object Object],[object Object]
Layout Verification ,[object Object],[object Object],[object Object],[object Object]
Layout Verification F. Simulations Pre-Layout Simulation - before layout work Post-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.
Layout Verification The complete design environment of Fill-Custom Design Design database – Cadence Design Framework II Circuit Editor – Text editor/Schematic editor ( S-edit , Composer) Circuit Simulator – SPICE, TSPICE , HSPICE Layout Editor – Cadence Virtuoso, Laker, L-edit Layout Verification Diva, Dracula, Calibre, Hercules
Concluding Remarks ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],It is EDA that pushes the IC design technology forward ! [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
SCNA Layout Rules [Ref.] John P. Uyemura, “Physical Design of CMOS Integrated Circuits Using L-EDIT”, PWS Publishing Company, 1995.
SCNA Layout Rules
SCNA Layout Rules
SCNA Layout Rules
SCNA Layout Rules
SCNA Layout Rules
LAB. 3 ,[object Object],[object Object]

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lect5_Stick_diagram_layout_rules

  • 1. VLSI Design and Layout Practice Lect5 – Stick Diagram & Scalable Design Rules Danny Wen-Yaw Chung Institute of Electronic Engineering Chung-Yuan Christian University Sept. 2008
  • 2.
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  • 7. B. Notations of the stick diagram
  • 8.
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  • 14.
  • 15. CMOS Transmission Gate The transmission gate Circuit schematic Stick diagram
  • 17. [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1 CMOS Stick Diagrams NAND
  • 18. < Exercise 1 > To draw the following circuitry by using a stick diagram
  • 19. < Exercise 2 > To draw the stick diagram and the schematic for the following layout
  • 20. CMOS Stick Diagrams [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1 NOR
  • 21. CMOS Inverter Mask Layout Min. spacing and line width consideration
  • 22.
  • 23. Lambda based design: half of technology since 1985. As technology changes with smaller dimensions, a simple change in the value of  can be used to produce a new mask set. All device mask dimensions are based on multiples of  , e.g., polysilicon minimum width = 2  . Minimum metal to metal spacing = 3  Lambda-based Design Rules 6  2  6   3  3 
  • 24. Active Contact and Surround Rule
  • 25. Potential Problem - Misalignment
  • 26. Potential Problem – Short between Source and Drain
  • 27. Degree of anisotropy A = 1 – r lat /r vert Where r  respective etch rates Physical Limitations
  • 28.
  • 29.
  • 30.
  • 31.
  • 32.
  • 33.
  • 34.
  • 36.
  • 39. SCMOS Design Rules [Ref]: 教育部顧問室 「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
  • 40.
  • 41.
  • 42.
  • 43.
  • 44. Layout Verification F. Simulations Pre-Layout Simulation - before layout work Post-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.
  • 45. Layout Verification The complete design environment of Fill-Custom Design Design database – Cadence Design Framework II Circuit Editor – Text editor/Schematic editor ( S-edit , Composer) Circuit Simulator – SPICE, TSPICE , HSPICE Layout Editor – Cadence Virtuoso, Laker, L-edit Layout Verification Diva, Dracula, Calibre, Hercules
  • 46.
  • 47. SCNA Layout Rules [Ref.] John P. Uyemura, “Physical Design of CMOS Integrated Circuits Using L-EDIT”, PWS Publishing Company, 1995.
  • 53.