Realisation de controlleur VGA(VHDL)

Rapport : Contrôleur d’affichage vidéo VGARéaliser par :AYARI YAHIA & DAHMANI MOHAMED2010/2011SommaireBut :Introduction :Description des machines à état :Décoder :Générateur de synchronisation :Synchro ligne :Synchro trame :Afficher :Description matérielle :Schéma RTL :Description en VHDL (code source) :MUX1 :ROM :RAM :MUX2 :Séquenceurs :Générateur de décodage :Gestionnaire d’affichage :Générateur de synchronisation :Générateur trameGénérateur ligne :Top module VGA :Les scenarios de test (TEST BENCH):Test MUXTest ROM:Test decoder:Test afficher :Test ligne :Test trame :Test VGA:Simulation:Fichier texte:Exemple de simulation:Rapport technique :Outils de développement :Conclusion : BUT : Notre projet sert à réaliser une propriété intellectuelle d’affichage vidéo VGA destiné au débogage hardware en environnement FPGA. Dans ce TP on va se familiariser avec un outil de développement hard trop connu XILINX, puis on va implémenter notre application sur une FPGA adéquate. Introduction : Il existe plusieurs modes pour la norme VGA, et nous allons utiliser celle dont la définition de l’image est de 640×480 dont les informations sont codées chacune sur un ensemble de bit. Le protocole VGA consiste à utiliser deux signaux de synchronisation horizontale SL et verticale ST pour pouvoir guider la manière d’afficher. Pour une qui parvient à tous les pixels de l’écran à une fréquence de 25 MHz (soit à une période de 40 ns). Le module d’affichage VGA lit une image à partir d’une mémoire et l’affiche sur un écran. Les contraintes à prendre en compte sont les contraintes de temps d’accès aux données des pixels et leur transmission sur un câble VGA dans les délais requis. D’autres difficultés se présentent aussi, surtout lorsque l’image en question stockée dans la mémoire est lue à partir d’un PC à travers un câble série. Dans ce cas, il faut gérer et organiser l’accès en lecture et en écriture à la mémoire par les différentes unités et en utilisant des autres modules de traitement et de gestion qui seront des extensions pour notre application et notre IP ; Cette IP étant intégré dans des applications matérielles sur FPGA permet de visualiser sur écran SVGA une ligne de 8 caractère des valeurs hexadécimaux à partir de 8 signaux en entré U0-U7 codés sur 4 bits. ST Module d’affichage de 16 Mots binaires à 4 bits SL25MHZ SPU<0> RVBU<7> SPECIFICATION EXTERNE D’IP En sortie : cette IP fournira des signaux de contrôle d’affichage vidéo : ST : Synchronisation de début d’une image (trame) affichée en temps réels. SL : Synchronisation de début d’une ligne. SP : Synchronisation de Transfer d’un pixel<<point image>>. RVB(Final) : signal résultat validé à chaque front montant d’horloge. La fréquence de rafraichissement doit être suffisante pour tromper la persistance de l’œil humaine, les pixels sont affichés séquentiellement par succession de lignes horizontaux de haut en bas, le balayage de ligne s’effectue de droite à gauche. Pour cette IP on choisie l’affichage SVGA SP=25 MHZ, SL=31.25 KHZ, ST=62. HZ On distingue les modules suivants : Chemin de données : Mux1 : multiplexeur des signaux Ui. ROM : permet de garder la police des caractères en mémorisant les fonts de ces caractères hexadécimaux de 0 à F. RAM : une mémoire en double port pour mémoriser le plan image dit bitmap. Mux2 : pour la sérialisation des mots binaire vers les signaux d’affichage. Séquenceurs : Gestion de décodage binaire : ce module ce module séquentielle à chaque début de trame il sert à indexer la Rom et la Ram pour pouvoir savoir d’où et où en va écrire. Gestion d’affichage : ce module génère le signal sortie et gère le nombre de colonne et de ligne de la trame lors de la l’écriture il est dirigé par le générateur de synchronisation. Gestion de synchronisation : ce module génère les synchro trame ST et les synchro ligne SL. C’est lui qui indique le début d’une trame ou celle d’une ligne. Description des machines à états : Décoder : Générateur de synchronisation : Synchro ligne : Synchro trame : Afficher : Description matérielle: Schema RTL Description en VHDL (code source): MUX1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX_8_1 is port( u0 : in STD_LOGIC_vector(3 downto 0); ----les données à afficher---- u1 : in STD_LOGIC_vector(3 downto 0); u2 : in STD_LOGIC_vector(3 downto 0); u3 : in STD_LOGIC_vector(3 downto 0); u4 : in STD_LOGIC_vector(3 downto 0); u5 : in STD_LOGIC_vector(3 downto 0); u6 : in STD_LOGIC_vector(3 downto 0); u7 : in STD_LOGIC_vector(3 downto 0); se : in STD_LOGIC_vector(2 downto 0); -----entrée selective----- ds : out STD_LOGIC_vector(3 downto 0)); -----sortie de MUX------ end MUX_8_1; architecture MUX_8_1 of MUX_8_1 is begin process(se,u0,u1,u2,u3,u4,u5,u6,u7) begin Case se is when quot;
000quot;
=> ds <= u0; when quot;
001quot;
010quot;
011quot;
100quot;
101quot;
110quot;
111quot;
=> ds <= u7; when others => ds <= quot;
0000quot;
; end case ; end process; end MUX_8_1; ROM ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:43:06 03/14/2011 -- Design Name: -- Module Name: ROM - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ROM is port( A: in std_logic_vector(9 downto 0); data:out std_logic); end ROM; architecture Behavioral of ROM is signal inter :std_logic_vector(63 downto 0):=(others => '0'); signal i:integer range 127 downto 0 :=0; signal j:integer range 63 downto 0 :=0; type police is array(127 downto 0) of std_logic_vector(7 downto 0); constant D : police := ( 0 => quot;
01110000quot;
, --0-- 1 => quot;
10001000quot;
, 2 => quot;
10001000quot;
, 3 => quot;
10001000quot;
, 4 => quot;
10001000quot;
, 5 => quot;
10001000quot;
, 6 => quot;
10001000quot;
, 7 => quot;
01110000quot;
, 8 => quot;
00100000quot;
, --1-- 9 => quot;
01100000quot;
, 10 => quot;
10100000quot;
, 11 => quot;
00100000quot;
, 12 => quot;
00100000quot;
, 13 => quot;
00100000quot;
, 14 => quot;
00100000quot;
, 15 => quot;
11111000quot;
, 16 => quot;
01110000quot;
, --2-- 17 => quot;
10001000quot;
, 18 => quot;
10001000quot;
, 19 => quot;
00010000quot;
, 20 => quot;
00100000quot;
, 21 => quot;
01000000quot;
, 22 => quot;
11111000quot;
, 23 => quot;
11111000quot;
, --3-- 24 => quot;
00001000quot;
, 25 => quot;
00001000quot;
, 26 => quot;
01111000quot;
, 27 => quot;
01111000quot;
, 28 => quot;
00001000quot;
, 29 => quot;
00001000quot;
, 30 => quot;
11111000quot;
, 31 => quot;
10000000quot;
, --4-- 32 => quot;
10000000quot;
, 33 => quot;
10010000quot;
, 34 => quot;
10010000quot;
, 35 => quot;
11111000quot;
, 36 => quot;
00010000quot;
, 37 => quot;
00010000quot;
, 38 => quot;
00010000quot;
, 39 => quot;
11111000quot;
, --5-- 40 => quot;
10000000quot;
, 41 => quot;
10000000quot;
, 42 => quot;
10000000quot;
, 43 => quot;
11111000quot;
, 44 => quot;
00001000quot;
, 45 => quot;
00001000quot;
, 46 => quot;
11111000quot;
, 47 => quot;
11111000quot;
, --6-- 48 => quot;
00001000quot;
, 49 => quot;
00001000quot;
, 50 => quot;
11111000quot;
, 51 => quot;
10001000quot;
, 52 => quot;
10001000quot;
, 53 => quot;
10001000quot;
, 54 => quot;
11111000quot;
, 55 => quot;
11111000quot;
, --7-- 56 => quot;
10001000quot;
, 57 => quot;
00001000quot;
, 58 => quot;
00001000quot;
, 59 => quot;
00010000quot;
, 60 => quot;
00100000quot;
, 61 => quot;
01000000quot;
, 62 => quot;
10000000quot;
, 63 => quot;
11111000quot;
, --8-- 64 => quot;
10001000quot;
, 65 => quot;
10001000quot;
, 66 => quot;
11111000quot;
, 67 => quot;
10001000quot;
, 68 => quot;
10001000quot;
, 69 => quot;
10001000quot;
, 70 => quot;
11111000quot;
, 71 => quot;
11111000quot;
, --9-- 72 => quot;
10001000quot;
, 73 => quot;
10001000quot;
, 74 => quot;
11111000quot;
, 75 => quot;
00001000quot;
, 76 => quot;
00001000quot;
, 77 => quot;
10001000quot;
, 78 => quot;
11111000quot;
, 79 => quot;
01110000quot;
, --A-- 80 => quot;
10001000quot;
, 81 => quot;
10001000quot;
, 82 => quot;
10001000quot;
, 83 => quot;
11111000quot;
, 84 => quot;
10001000quot;
, 85 => quot;
10001000quot;
, 86 => quot;
10001000quot;
, 87 => quot;
11111000quot;
, --B-- 88 => quot;
10001000quot;
, 89 => quot;
10001000quot;
, 90 => quot;
11111000quot;
, 91 => quot;
10001000quot;
, 92 => quot;
10001000quot;
, 93 => quot;
10001000quot;
, 94 => quot;
11111000quot;
, 95 => quot;
11111000quot;
, --C-- 96 => quot;
10001000quot;
, 97 => quot;
10000000quot;
, 98 => quot;
10000000quot;
, 99 => quot;
10000000quot;
, 100=> quot;
10000000quot;
, 101=> quot;
10000000quot;
, 102=> quot;
10000000quot;
, 103=> quot;
11111000quot;
, 104=> quot;
11110000quot;
, --D-- 105=> quot;
10001000quot;
, 106=> quot;
10001000quot;
, 107=> quot;
10001000quot;
, 108=> quot;
10001000quot;
, 109=> quot;
10001000quot;
, 110=> quot;
10001000quot;
, 111=> quot;
11110000quot;
, 112=> quot;
11111000quot;
, --E-- 113=> quot;
10001000quot;
, 114=> quot;
10000000quot;
, 115=> quot;
10000000quot;
, 116=> quot;
11110000quot;
, 117=> quot;
10000000quot;
, 118=> quot;
10001000quot;
, 119=> quot;
11111000quot;
, 120=> quot;
11111000quot;
, --F-- 121=> quot;
10001000quot;
, 122=> quot;
10000000quot;
, 123=> quot;
11110000quot;
, 124=> quot;
10000000quot;
, 125=> quot;
10000000quot;
, 126=> quot;
10000000quot;
, 127=> quot;
10000000quot;
); begin i <= 8*(to_integer ( unsigned (A(3 downto 0)))); j <= (to_integer ( unsigned (A(9 downto 4)))); inter(7 downto 0) <= D(i); inter(39 downto 32) <= D(i+4); inter(15 downto 8) <= D(i+1); inter(47 downto 40) <= D(i+5); inter(23 downto 16) <= D(i+2); inter(55 downto 48) <= D(i+6); inter(31 downto 24) <= D(i+3); inter(63 downto 56) <= D(i+7); data <= inter(j); end Behavioral; RAM ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:40:18 03/15/2011 -- Design Name: -- Module Name: RAM - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity RAM_VGA is port( A: in std_logic_vector(8 downto 0); R: in std_logic_vector(8 downto 0); Din,clk,WR:in std_logic; Dout:out std_logic); end RAM_VGA; architecture Behavioral of RAM_VGA is signal RAM_MEM:std_logic_vector(511 downto 0); begin write_process: Process(clk,WR) begin if(clk' event and clk='1') then if WR='1' then (RAM_MEM(to_integer(unsigned(A)))) <= Din; end if; end if; end process; read_process: process(R,wr,RAM_MEM) begin if(wr='0')then Dout <= (RAM_MEM(to_integer(unsigned(R)))); end if; end process; end Behavioral; MUX2 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity MUX_2_1 is port( enter : in STD_LOGIC; ----les données à afficher---- mass : in STD_LOGIC; se : in std_logic; -----entrée selective----- final : out STD_LOGIC); -----sortie de MUX------ end MUX_2_1; architecture Behavioral of MUX_2_1 is begin process (se,enter,mass) begin Case se is when '0' => final <= mass; when '1' => final <= enter; when others => final <= '0' ; end case ; end process; end Behavioral; Sequenceurs Gestionneur de decodage library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity decoder is port( st,clk:in std_logic; wr:out std_logic; sortie:out std_logic_vector(8 downto 0)); end decoder; architecture Behavioral of decoder is type state is(repot,copier,fin_t); signal etat:state; signal inter:std_logic_vector(8 downto 0):=(others => '0'); begin process(clk) begin if(clk'event and clk='1') then case etat is when repot => ---repot-- inter<=quot;
000000000quot;
; wr<='0'; if st='0' then etat<= copier; end if; when copier => sortie<=inter; ---copier -- inter<=inter+quot;
000000001quot;
; wr<='1'; if inter=quot;
111111111quot;
then etat<= fin_t; end if; when fin_t => ---fin_t-- wr<='0'; if st='1' then etat<= repot; end if; end case; end if; end process; end Behavioral; Gestionnaire d’affichage library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity affichage is port( clk,ft,fl:in std_logic; nl:out std_logic_vector( 2 downto 0); nc:out std_logic_vector( 5 downto 0); noir:out std_logic); end affichage; architecture Behavioral of affichage is type state is(repot,attendre_fl,ligne,incrementation,fin_ligne,fin_trame); signal etat:state; signal nc1:std_logic_vector( 5 downto 0):=(others => '0'); signal nl1:std_logic_vector( 3 downto 0):=(others => '0'); begin process(clk) begin if (clk' event and clk='1') then case etat is when repot => ---repot-- noir<='0'; nc1<=quot;
000000quot;
; nl1<=quot;
0000quot;
; if ft='1' then etat<= attendre_fl; end if; when attendre_fl => ---attendre fenetre ligne-- noir<='0'; nc1<=quot;
000000quot;
; if fl='1' then etat<= ligne; end if; when ligne => ---affichage d'une ligne--- noir<='1'; nc<=nc1; nc1<=nc1+quot;
000001quot;
; if nc1=quot;
111111quot;
then etat<= incrementation; end if; when incrementation => ---incrementation de nombre de ligne---- noir<='0'; nc1<=quot;
000000quot;
; nl1<=nl1+quot;
0001quot;
; nl<=nl1(2 downto 0); if nl1=quot;
1000quot;
then --etat<=fin_ligne; etat<=fin_trame; end if; if nl1/=quot;
1000quot;
then etat<= fin_ligne; end if; when fin_ligne => ----fin ligne------------- noir<='0'; if fl='0' then etat<= attendre_fl; end if; when fin_trame => ----fin trame---- noir<='0'; if ft='0' then etat<= repot; end if; end case; end if; end process; end Behavioral; Générateur de synchronisation Générateur ligne ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:32:25 03/17/2011 -- Design Name: -- Module Name: generateur_ligne - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity generateur_ligne is port( clk: in std_logic; sl,fl:out std_logic ); end generateur_ligne; architecture Behavioral of generateur_ligne is type state is(deb,tsl,gap1,gap2,ligne); signal etat : state; signal n : integer range 0 to 800; begin process(clk) begin if (clk' event and clk='1') then case etat is when deb => ---debut-- n<= 800; sl<='1'; fl<='0'; etat<= tsl; when tsl => ---retour en ligne-- n<= n-1; sl<='0'; fl<='0'; if n=740 then etat<= gap1; end if; when gap1 => ---debut d'une fenetre ligne--- n<=n-1; sl<='1'; fl<='0'; if n=690 then etat<= ligne; end if; when ligne => ---ligne à écrire ---- n<=n-1; sl<='1'; fl<='1'; if n=50 then etat<= gap2; end if; when gap2 => ----fenetre ligne (blanc aprés ligne)---- n<=n-1; sl<='0'; fl<='0'; if n=0 then etat<= deb; end if; end case; end if; end process; end Behavioral; Générateur trame ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:11:39 03/29/2011 -- Design Name: -- Module Name: generateur_trame - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity generateur_trame is port( sl:in std_logic; st,ft:out std_logic); end generateur_trame; architecture Behavioral of generateur_trame is type state is(deb,tst,gapt1,page,gapt2); signal etat:state; signal n : integer range 0 to 503; begin process(sl) begin if (sl='0') then case etat is when deb => ---debut----- n<=503; st<='1'; ft<='0'; etat<= tst; when tst => ---nouvelle trame-- n<= n-1; st<='0'; ft<='0'; if n=495 then etat<= gapt1; end if; when gapt1 => ---debut d'une fenetre trame--- n<=n-1; st<='1'; ft<='0'; if n=490 then etat<= page; end if; when page => ---trame à écrire ---- n<=n-1; st<='1'; ft<='1'; if n=10 then etat<= gapt2; end if; when gapt2 => ----fenetre trame (blanc aprés les lignes)---- n<=n-1; st<='1'; ft<='0'; if n=0 then etat<= deb; end if; end case; end if; end process; end Behavioral; Top module VGA ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:13:09 04/09/2011 -- Design Name: -- Module Name: top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top is port( uu0 : in std_logic_vector(3 downto 0); uu1 : in std_logic_vector(3 downto 0); uu2 : in std_logic_vector(3 downto 0); uu3 : in std_logic_vector(3 downto 0); uu4 : in std_logic_vector(3 downto 0); uu5 : in std_logic_vector(3 downto 0); uu6 : in std_logic_vector(3 downto 0); uu7 : in std_logic_vector(3 downto 0); clk_25MHZ: in std_logic; sl,st:out std_logic; final:out std_logic ); end top; architecture top of top is COMPONENT ROM PORT( A : IN std_logic_vector(9 downto 0); data : OUT std_logic ); END COMPONENT; COMPONENT RAM_VGA port( A: in std_logic_vector(8 downto 0); R: in std_logic_vector(8 downto 0); Din,clk,WR:in std_logic; Dout:out std_logic ); END COMPONENT; COMPONENT MUX_8_1 PORT( u0 : in STD_LOGIC_vector(3 downto 0); u1 : in STD_LOGIC_vector(3 downto 0); u2 : in STD_LOGIC_vector(3 downto 0); u3 : in STD_LOGIC_vector(3 downto 0); u4 : in STD_LOGIC_vector(3 downto 0); u5 : in STD_LOGIC_vector(3 downto 0); u6 : in STD_LOGIC_vector(3 downto 0); u7 : in STD_LOGIC_vector(3 downto 0); se : in STD_LOGIC_vector(2 downto 0); ds : out STD_LOGIC_vector(3 downto 0)); END COMPONENT; COMPONENT MUX_2_1 PORT( enter : in STD_LOGIC; mass : in STD_LOGIC; se : in std_logic; final : out STD_LOGIC); END COMPONENT; COMPONENT affichage PORT( clk : IN std_logic; ft : IN std_logic; fl : IN std_logic; nl : OUT std_logic_vector(2 downto 0); nc : OUT std_logic_vector(5 downto 0); noir : OUT std_logic ); END COMPONENT; COMPONENT decoder PORT( st : IN std_logic; clk : IN std_logic; wr : OUT std_logic; sortie : OUT std_logic_vector(8 downto 0) ); END COMPONENT; COMPONENT generateur_trame PORT( sl : IN std_logic; st : OUT std_logic; ft : OUT std_logic ); END COMPONENT; COMPONENT generateur_ligne PORT( clk : IN std_logic; sl : OUT std_logic; fl : OUT std_logic ); END COMPONENT; signal ds1:std_logic_vector(3 downto 0); signal sortie1:std_logic_vector(8 downto 0); signal data1:std_logic; signal WR1:std_logic; signal DOUT1:std_logic; signal noir1:std_logic; signal nc1:std_logic_vector( 5 downto 0); signal nl1:std_logic_vector( 2 downto 0); signal ft1:std_logic; signal fl1:std_logic; signal st1:std_logic; signal sl1:std_logic; signal mass:std_logic; begin mass<='0'; a1:MUX_8_1 PORT MAP( u0=>uu0, u1=>uu1, u2=>uu2, u3=>uu3, u4=>uu4, u5=>uu5, u6=>uu6, u7=>uu7, se=>sortie1(8 downto 6), ds=>ds1 ); a11: MUX_2_1 PORT MAP ( enter =>DOUT1, mass => mass, se => noir1, final=> final ); a2:ROM PORT MAP ( A(3 downto 0)=> ds1, A(9 downto 4)=>sortie1(5 downto 0), data => data1 ); a3:RAM_VGA port MAP( A=>sortie1, R(8 downto 6)=>nc1(5 downto 3), R(5 downto 3)=>nl1, R(2 downto 0)=>nc1(2 downto 0), Din=>data1, clk=>clk_25MHZ, WR=>WR1, Dout=>DOUT1 ); a4:affichage PORT MAP ( clk => clk_25MHZ, ft => ft1, fl => fl1, nl => nl1, nc => nc1, noir => noir1 ); a5:decoder PORT MAP ( st => st1, clk => clk_25MHZ, wr => WR1, sortie => sortie1 ); a6:generateur_trame PORT MAP ( sl => sl1, st => st1, ft => ft1 ); a7:generateur_ligne PORT MAP ( clk => clk_25MHZ, sl => sl1, fl => fl1 ); sl<=sl1; st<=st1; end top; Les scenarios de test (les tests bench): Test MUX : -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:31:03 03/30/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_MUX.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: MUX_8_1 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_MUX IS END test_MUX; ARCHITECTURE behavior OF test_MUX IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MUX_8_1 PORT( u0 : IN std_logic_vector(3 downto 0); u1 : IN std_logic_vector(3 downto 0); u2 : IN std_logic_vector(3 downto 0); u3 : IN std_logic_vector(3 downto 0); u4 : IN std_logic_vector(3 downto 0); u5 : IN std_logic_vector(3 downto 0); u6 : IN std_logic_vector(3 downto 0); u7 : IN std_logic_vector(3 downto 0); se : IN std_logic_vector(2 downto 0); ds : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal u0 : std_logic_vector(3 downto 0) := quot;
1011quot;
; signal u1 : std_logic_vector(3 downto 0) := (others => '0'); signal u2 : std_logic_vector(3 downto 0) := (others => '0'); signal u3 : std_logic_vector(3 downto 0) := (others => '0'); signal u4 : std_logic_vector(3 downto 0) := (others => '0'); signal u5 : std_logic_vector(3 downto 0) := (others => '0'); signal u6 : std_logic_vector(3 downto 0) := (others => '0'); signal u7 : std_logic_vector(3 downto 0) := (others => '0'); signal se : std_logic_vector(2 downto 0) := quot;
000quot;
; --Outputs signal ds : std_logic_vector(3 downto 0); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name BEGIN -- Instantiate the Unit Under Test (UUT) uut: MUX_8_1 PORT MAP ( u0 => u0, u1 => u1, u2 => u2, u3 => u3, u4 => u4, u5 => u5, u6 => u6, u7 => u7, se => se, ds => ds ); END; Test ROM : -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:49:36 03/15/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/ROM_TEST.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: ROM -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY ROM_TEST IS END ROM_TEST; ARCHITECTURE behavior OF ROM_TEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ROM PORT( A : IN std_logic_vector(9 downto 0); data : OUT std_logic ); END COMPONENT; --Inputs signal A : std_logic_vector(9 downto 0) := quot;
1111101111quot;
; --Outputs signal data : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name BEGIN -- Instantiate the Unit Under Test (UUT) uut: ROM PORT MAP ( A => A, data => data ); END; Test decoder -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:19:06 03/30/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_decoder.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: decoder -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_decoder IS END test_decoder; ARCHITECTURE behavior OF test_decoder IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT decoder PORT( st : IN std_logic; clk : IN std_logic; wr : OUT std_logic; sortie : OUT std_logic_vector(8 downto 0) ); END COMPONENT; --Inputs signal st : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal wr : std_logic; signal sortie : std_logic_vector(8 downto 0); -- Clock period definitions constant clk_period : time := 0.002 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: decoder PORT MAP ( st => st, clk => clk, wr => wr, sortie => sortie ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; -- insert stimulus here wait; end process; END; Test afficher -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:26:36 03/29/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_affichage.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: affichage -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_affichage IS END test_affichage; ARCHITECTURE behavior OF test_affichage IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT affichage PORT( clk : IN std_logic; ft : IN std_logic; fl : IN std_logic; nl : OUT std_logic_vector(2 downto 0); nc : OUT std_logic_vector(5 downto 0); noir : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal ft : std_logic := '1'; signal fl : std_logic := '1'; --Outputs signal nl : std_logic_vector(2 downto 0); signal nc : std_logic_vector(5 downto 0); signal noir : std_logic; -- Clock period definitions constant clk_period : time := 0.002 ns; signal n:integer range 0 to 100; BEGIN -- Instantiate the Unit Under Test (UUT) uut: affichage PORT MAP ( clk => clk, ft => ft, fl => fl, nl => nl, nc => nc, noir => noir ); -- Clock process definitions clk_process :process begin fl<='1'; clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; fl<='0'after 0.137 ns; end process; END; Test_ligne -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:51:19 03/17/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/tester_ligne.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: generateur_ligne -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tester_ligne IS END tester_ligne; ARCHITECTURE behavior OF tester_ligne IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT generateur_ligne PORT( clk : IN std_logic; sl : OUT std_logic; fl : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; --Outputs signal sl : std_logic; signal fl : std_logic; -- Clock period definitions constant clk_period : time := 0.002 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: generateur_ligne PORT MAP ( clk => clk, sl => sl, fl => fl ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; -- insert stimulus here wait; end process; END; Test_trame -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:19:18 03/29/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_trame.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: generateur_trame -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_trame IS END test_trame; ARCHITECTURE behavior OF test_trame IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT generateur_trame PORT( sl : IN std_logic; st : OUT std_logic; ft : OUT std_logic ); END COMPONENT; --Inputs signal sl : std_logic := '0'; --Outputs signal st : std_logic; signal ft : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant clk : time := 0.002 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: generateur_trame PORT MAP ( sl => sl, st => st, ft => ft ); -- Clock process definitions process begin sl <= '0'; wait for clk/2; sl <= '1'; wait for clk/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk*10; -- insert stimulus here wait; end process; END Test_VGA -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:42:38 04/10/2011 -- Design Name: -- Module Name: C:/Users/yahya/Desktop/project hard/VGA/test_top.vhd -- Project Name: VGA -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: top -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee ; use std.textio.all; USE ieee.std_logic_1164.all ; LIBRARY std; use IEEE.std_logic_textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY test_top IS END test_top; ARCHITECTURE behavior OF test_top IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT top PORT( uu0 : IN std_logic_vector(3 downto 0); uu1 : IN std_logic_vector(3 downto 0); uu2 : IN std_logic_vector(3 downto 0); uu3 : IN std_logic_vector(3 downto 0); uu4 : IN std_logic_vector(3 downto 0); uu5 : IN std_logic_vector(3 downto 0); uu6 : IN std_logic_vector(3 downto 0); uu7 : IN std_logic_vector(3 downto 0); clk_25MHZ : IN std_logic; sl : OUT std_logic; st : OUT std_logic; final : OUT std_logic ); END COMPONENT; --Inputs signal uu0 : std_logic_vector(3 downto 0) := quot;
1111quot;
; signal uu1 : std_logic_vector(3 downto 0) := quot;
0001quot;
0000quot;
0000quot;
0000quot;
0000quot;
0000quot;
0000quot;
; signal clk_25MHZ : std_logic := '0'; --Outputs signal sl : std_logic; signal st : std_logic; signal final : std_logic; -- Clock period definitions constant clk_25MHZ_period : time := 40 ps; signal a:integer range 66 downto 0 :=0; signal b:integer range 2 downto 0 :=0; signal deb1:integer range 1 downto 0 :=0; signal deb2:integer range 1 downto 0 :=0; signal deb3:integer range 1 downto 0 :=0; signal deb4:integer range 1 downto 0 :=0; signal deb5:integer range 1 downto 0 :=0; signal deb6:integer range 1 downto 0 :=0; signal deb7:integer range 1 downto 0 :=0; signal deb8:integer range 1 downto 0 :=0; signal d:integer range 8 downto 0 :=1; type TAB is array(0 to 161) of bit; signal T : TAB; BEGIN -- Instantiate the Unit Under Test (UUT) uut: top PORT MAP ( uu0 => uu0, uu1 => uu1, uu2 => uu2, uu3 => uu3, uu4 => uu4, uu5 => uu5, uu6 => uu6, uu7 => uu7, clk_25MHZ => clk_25MHZ, sl => sl, st => st, final => final ); -- Clock process definitions clk_25MHZ_process :process begin clk_25MHZ <= '0'; wait for clk_25MHZ_period/2; clk_25MHZ <= '1'; wait for clk_25MHZ_period/2; --fixer les debut des ligne pour l'affichage dans notre fichier texte--- deb1<=1 after 293.280 ns; deb2<=1 after 325.380 ns; deb3<=1 after 357.460 ns; deb4<=1 after 389.540 ns; deb5<=1 after 421.620 ns; deb6<=1 after 453.700 ns; deb7<=1 after 485.780 ns; deb8<=1 after 517.860 ns; end process; --ecriture de resultat de notre controleur VGA dans une fichier TXT----- ECRITURE: process(clk_25MHZ,d,deb1,deb2,deb3,deb4,deb5,deb6,deb7,deb8) variable L: line; file SORTIES: text open WRITE_MODE is quot;
C:sersahyaesktopeses.txtquot;
; begin if(clk_25MHZ' event and clk_25MHZ='1') then if(deb1=1 and d=1)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=2; end if; end if; end if; if(deb2=1 and d=2)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=3; end if; end if; end if; if(deb3=1 and d=3)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=4; end if; end if; end if; if(deb4=1 and d=4)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=5; end if; end if; end if; if(deb5=1 and d=5)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=6; end if; end if; end if; if(deb6=1 and d=6)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=7; end if; end if; end if; if(deb7=1 and d=7)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); -- écriture de la ligne dans le fichier d<=8; end if; end if; end if; if(deb8=1 and d=8)then if(final='0') then T(a)<='0'; a<=a+1; end if; if(final='1') then T(a)<='1'; a<=a+1; b<=1; end if; if(a=66)then a<=0; if(b=1)then b<=0; for i in 0 to 66 loop write(L, T(i)); end loop; writeline(SORTIES, L); end if; end if; end if; end if; end process ECRITURE; END; Simulation Fichier: Simulation (0, 0, 0, 0, 0, 0, 0, 0): Simulation (F, 1, 0, 0, 0, 0, 0, 0): Rapport technique: Outil de développement utilisé: Logiciel : Xilinx est une entreprise américaine de semi-conducteurs. Inventeur du FPGA, Xilinx fait partie des plus grandes entreprises spécialisées dans le développement et la commercialisation de composants logiques programmables, et des services associés tels que les logiciels de CAO électroniques ; blocs de propriété intellectuelle réutilisables et formation. Langage : VHDL est un langage de description matériel destiné à représenter le comportement ainsi que l'architecture d’un système électronique numérique. Son nom complet est VHSIC Hardware Description Langage. L'intérêt d'une telle description réside dans son caractère exécutable : une spécification décrite en VHDL peut être vérifiée par simulation, avant que la conception détaillée ne soit terminée. En outre, les outils de conception assistée par ordinateur permettant de passer directement d'une description fonctionnelle en VHDL à un schéma en porte logique ont révolutionné les méthodes de conception des circuits numériques, ASIC ou FPGA. Conclusion: Le but de ce projet est d’exploiter le FPGA Spartan 3 de Xilinx pour faire des applications basiques d’entrée sortie pour passer par la suite à des architectures relativement complexes rassemblant plusieurs composants qu’il faut synchroniser et gérer l’accès à la mémoire. Au cours de ce projet, nous avons fait l’implantation en VHDL de circuits basiques, à savoir le module VGA et ces spécifications. Cependant, nous avons pu valider l’architecture de l’affichage sur écran VGA en utilisant des méthodes de simulations qui peuvent réaliser le même résultat qu’implémenter notre application sur carte. Mais nous sommes familiarisés avec les outils de développement hard. Notre ROM ne contient pas tous les caractères que l'utilisateur peut saisir (restriction sur les HEXA) donc on peut penser à des modules intermédiaires de traitements qui peuvent jouer le rôle de constructeur de nouveaux caractères à partir de notre ROM suite à un nouveau codage que l'on peut définir également.

Realisation de controlleur VGA(VHDL)

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (20)

Similar to Realisation de controlleur VGA(VHDL)

Similar to Realisation de controlleur VGA(VHDL) (20)

Realisation de controlleur VGA(VHDL)