13. HOME WORK 0
• INSTAL THE ACTIVE HDL=100
• MAIN OF VHDL
Main Error
14. Introduction
• A field-programmable gate array (FPGA) is an
integrated circuit designed to be configured by a
customer or a designer after manufacturing – hence
"field-programmable".
• The FPGA configuration is generally specified using a
hardware description language (HDL), similar to that
used for an application-specific integrated circuit
(ASIC).
24. HOME WORK 1
• 1 ISI ARTICLE : Abstract
• Design and Idea about a “ Kitchen DEVICE”
For
Mother's Day :)
• Mother's Day is a celebration honoring the mother of the family, as well as motherhood,
maternal bonds, and the influence of mothers in society. It is celebrated on various days
in many parts of the world, most commonly in the months of February or everyday of the
week
31. HOME WORK 2
• WHAT IS :
• HALF ADDER=25
• FULL ADDER=25
• DECODER=25
• ENCODER=25
32. HOME WORK 3
• WHAT IS :
• CPU
• BIT OF CPU /8/16/64 BIT
• COMPONENT OF CPU
• ALUCURIGISTER
33. VHDL
• What is VHDL?
V H I S C Very High Speed Integrated Circuit
Hardware
Description
Language
IEEE Standard 1076-1993
34. History of VHDL
• Designed by IBM, Texas Instruments, and Intermetrics as part of
the DoD funded VHSIC program
• Standardized by the IEEE in 1987: IEEE 1076-1987
• Enhanced version of the language defined in 1993: IEEE 1076-
1993
• Additional standardized packages provide definitions of data
types and expressions of timing data
o IEEE 1164 (data types)
o IEEE 1076.3 (numeric)
o IEEE 1076.4 (timing)
35. Usage
• Descriptions can be at different levels of abstraction
o Switch level: model switching behavior of transistors
o Register transfer level: model combinational and
sequential logic components
o Instruction set architecture level: functional behavior of
a microprocessor
• Descriptions can used for
o Simulation
• Verification, performance evaluation
o Synthesis
• First step in hardware design
36. Digital System Design Flow
Requirements
Functional Design
Register Transfer
Level Design
Logic Design
Circuit Design
Physical Design
Description for Manufacture
Behavioral Simulation
RTL Simulation
Validation
Logic Simulation
Verification
Timing Simulation
Circuit Analysis
Design Rule Checking
Fault Simulation
• Design flows operate at multiple
levels of abstraction
• Need a uniform description to
translate between levels
• Increasing costs of design and
fabrication necessitate greater
reliance on automation via CAD
tools
– $5M - $100M to design new
chips
– Increasing time to market
pressures
38. 38
A VHDL program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ABorC is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
F : out std_logic);
end ABorC;
architecture arch of ABorC is
signal X : std_logic;
begin
X <= A and B after 1 ns;
F <= X or C after 1 ns;
end;
39. 39
Operations that can be performed on type integer. See SG p 36, DG p 35
Use parentheses to force
desired
Precedence.
40. 40
Constants
constant CONST_NAME: <type_spec> := <value>;
-- Examples of Declaration of Constants:
constant GO: BOOLEAN := TRUE;
constant Max: INTEGER := 31;
constant HexMax: INTEGER := 16#FF#; -- hex (base 16) integer
constant ONE: BIT := '1';
constant S0: BIT_VECTOR (3 downto 0) := "0000";
constant S1: bit_vector(15 downto 0) := X"AB3F“; -- hex string
constant HiZ: STD_LOGIC := 'Z'; -- Here Z is high impedance.
constant Ready: STD_LOGIC_VECTOR (3 downto 0) := "0-0-";
-- 0’s & don’t cares
Note: VHDL is not case sensitive. -- is used for comments.
• BOOLEAN, INTEGER, BIT, etc are examples of predefined VHDL types.
o VHDL is a strongly typed language.
o Cannot for example directly assign a bit or std_logic value to an integer type
41. 41
Variables
VAR_NAME := <expression>;
-- example
Count := 10;
Vbit := '0';
• Declaration
variable VAR_NAME: <type_spec>;
-- example:
variable Test: BOOLEAN;
variable Count: INTEGER range 0 to 31 := 15; -- Set initial value to
15.
variable vBIT: BIT;
variable VAR: BIT_VECTOR (3 downto 0);
variable VAR_X: STD_LOGIC := ‘0’; -- Set initial value to ‘0’.
variable VAR_Y: STD_LOGIC_VECTOR (0 to 3);
42. 42
Signals
SIG_NAME <= <expression>;
-- Examples
BitX <= ‘1’;
• Declaration
signal SIG_NAME: <type_spec>;
-- example:
signal Flag: BOOLEAN := TRUE; -- TRUE is the initial vlaue
signal intX: INTEGER range 0 to 31;
signal BitX: BIT := ‘1’;
signal Control_Bus: BIT_VECTOR (3 downto 0);
signal X: STD_LOGIC;
signal Y: STD_LOGIC_VECTOR (0 to 3) := “0000”;
43. 43
VHDL example EX 1
--EX1.vhd
ENTITY tb is END tb;
ARCHITECTURE test OF tb IS
signal X : BIT;
BEGIN
X <= not X after 10 ns;
END test;
44. 44
--EX2.vhd
ENTITY tb is END tb;
ARCHITECTURE test OF tb IS
signal X, Y : BIT;
BEGIN
X <= not X after 10 ns;
Y <= '1' after 5 ns, '0' after 12 ns, '1' after 25 ns;
END test;
45. 45
std_logic_1164 multi-
value logic system
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
46. 46
And Or gate in VHDL example
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ABorC is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic; F : out std_logic);
end ABorC;
architecture arch of ABorC is
signal X : std_logic;
begin
X <= A and B after 1 ns;
F <= X or C after 1 ns;
end;
1
2
3
C
FB
X
A
1
2
3
47. 47
Process
• Process statements occur within an architecture.
• The syntax for a process is:
LABEL1: -- optional label
process (signal_name, …) is
-- declarations
begin
-- sequential statements
end process LABEL1;
48. 48
Process example
• Without process statements
architecture ex_arc of ex4 is
signal X: BIT;
signal Y: BIT;
signal Z, V, W: BIT;
Begin
-- concurrent signals assignments
X <= not X after 10 ns;
Y <= not Y after 25 ns;
Z <= X and Y after 2 ns;
V <= (Z xor not W) nand X after 3
ns;
W <= X or Y after 1 ns;
end architecture ex_arc;
• With process statements
Process(X) begin
X <= not X after 10 ns;
End process;
P2: process(y) begin
Y <= not Y after 25 ns;
End process P2;
P3: Process(X,Y,Z,W)
begin
Z <= X and Y after 2 ns;
V <= (Z xor not W) nand X after 3
ns;
End process P3;
P4: process(X,Y) begin
W <= X or Y after 1 ns;
End process P4;
49. Basic Structure of a VHDL File
• Entity
o Entity declaration: interface
to outside world; defines
input and output signals
o Architecture: describes the
entity, contains processes,
components operating
concurrently
50. Entity Declaration
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;
• NAME_OF_ENTITY: user defined
• signal_names: list of signals (both input
and output)
• mode: in, out, buffer, inout
• type: boolean, integer, character,
std_logic
52. Entity Examples …
entity half_adder is
port(
x,y: in std_logic;
sum, carry: out std_logic);
end half_adder;
Half ADDER
X
Y
SUM
CARRY
53. Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(
x,y: in std_logic;
sum, carry: out std_logic);
end half_adder;
architecture myadd of half_adder is
begin
sum <= x xor y;
carry <= x and y;
end myadd;
54. Entity Examples …
entity FULL_adder is
port(
A, B, C: in std_logic;
sum, carry: out std_logic);
end half_adder;
FULL ADDER
A
B
C
SUM
CARRY
55. Architecture Examples: Behavioral Description
• Entity FULLADDER is
port ( A, B, C: in std_logic;
SUM, CARRY: in std_logic);
end FULLADDER;
• Architecture CONCURRENT of FULLADDER is
begin
SUM <= A xor B xor C after 5 ns;
CARRY <= (A and B) or (B and C) or (A and C)
after 3 ns;
end CONCURRENT;
56. Architecture Examples: Structural Description …
• architecture STRUCTURAL of FULLADDER is
signal S1, C1, C2 : bit;
component HA
port (I1, I2 : in bit; S, C : out bit);
end component;
component OR
port (I1, I2 : in bit; X : out bit);
end component;
begin
INST_HA1 : HA port map (I1 => B, I2 => C, S => S1, C => C1);
INST_HA2 : HA port map (I1 => A, I2 => S1, S => SUM, C => C2);
INST_OR : OR port map (I1 => C2, I2 => C1, X => CARRY);
end STRUCTURAL;
I1 S
HA
I2 C
I1 S
HA
I2 C I1
OR
I2 x
A
C
B
CARRY
SUM
S1
C1
C2
58. 58
U1: entity work.or3 port map
(A => AB, B => ACin , C => BCin , F => Cout);
U2: entity work.and2 port map
(A => A, B => B, F => AB);
U3: entity work.and2 port map
(A => B, B => Cin, F => BCin);
U4: entity work.and2 port map
(A => A, B => Cin, F => ACin);
U5: entity work.xor2 port map (A, B, AxorB);
U6: entity work.xor2 port map (Cin, AxorB, S);
AB
B
A
U5
XOR2
F
A
B
ACin
Cin
Cout
Cin
A
B
U4
AND2
F
A
B
U3
AND2
F
A
B
BCin
U6
XOR2
F
A
B S
U1
OR3
F
A
B
C
AxorB
U2
AND2
F
A
B
62. VHDL Code
-- STEP ONE
library ieee;
use ieee.std_logic_1164.all;
-- STEP TWO
entity PR1 is
port(
A,B,C: in std_logic;
F: out std_logic);
end PR1;
-- STEP THREE
architecture PRa of PR1 is
begin
Signal x,y,z; std_logic_vector (3 downto 0);
x <= a and b;
y <= a and c;
z <= b and c;
F <= x or y or z;
end PRa;
68. 4 to 1 MUX
library ieee;
use ieee.std_logic_1164.all;
-- 4 to 1 mux
entity mymux is
port (A, B, C, D : in
std_logic_vector(0 to 3);
Sel : in
std_logic_vector ( 0 to 1
);
Q : out
std_logic_vector(0 to 3) );
end mymux;
Library you need to include
Comment
entity “name_of_entity” is
port(all your input and output
signals);
end “name_of_entity”;
69. 4 to 1 MUX
architecture mux4 of mymux is
constant delay : time := 100 ns;
begin
mux_proc : process ( A, B, C, D, Sel )
variable temp :
std_logic_vector(0 to 3);
begin
case Sel is
when "00" => temp := A;
when "01" => temp := B;
when "10" => temp := C;
when "11" => temp := D;
when others => temp :=
"XXXX";
end case;
Q <= temp after delay;
end process mux_proc;
end mux4;
mux4 is the name of my
architecture
Declaration of time as a constant
begin the architecture
Process mux_proc is initialized
Variable temp is declared
begin process mux_proc
case on the Sel singal
If anything else then temp is don’t
care
If there was a delay on the mux
end process
end architecture
70. TestBench for 4 to 1 MUX
library ieee;
use ieee.std_logic_1164.all;
entity mux_testbench is
end mux_testbench;
architecture test of mux_testbench
is
signal A : std_logic_vector(0 to 3);
signal B: std_logic_vector(0 to 3);
signal C: std_logic_vector(0 to 3);
signal D: std_logic_vector(0 to 3);
signal Sel: std_logic_vector(0 to 1);
signal Q: std_logic_vector(0 to
3);
still have to begin with entity
end the entity
test is the name of the
architecture
the signals have to be the same
as the port signals in your entity
declaration of the program you
want to test.
71. TestBench for 4 to 1 MUX
component mymux is
port (A, B, C, D : in
std_logic_vector(0to3);
Sel : in std_logic_vector ( 0 to 1 );
Q : out std_logic_vector(0 to 3));
end component;
begin
test_mux: mymux
port map( A =>
A , B => B,
C => C ,
D => D,
Sel => Sel,
Q => Q );
This component declaration tells
us that we have 5 inputs
A,B,C,D and Sel; we also
have one output Q
The port map is used to link the
signal A from your VHDL
program to the signal A in
your testbench
Used incase you want to use
different names
72. TestBench for 4 to 1 MUX
test_process: process
begin A<="1010";
B<="1011";
C<="1100";
D<="1101";
Sel<="00";
wait for 500 ns;
Sel<="01";
wait for 500 ns;
Sel<="10";
wait for 500 ns;
Sel<="11";
wait for 500 ns;
end process;
end test;
initialize your signal
when Sel is 00 it should let A
come through on Q with a
delay of 100ns
when Sel is 01 Q should be B
end the process test_process
end the test
74. 8 – Bit Shifter
-- 8-Bit Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port (CLK, RST, LOAD : in
bit;
Data : in bit_vector(0 to
7);
Q : out bit_vector(0 to
7));
end rotate;
Comment
Library you need to include
entity “name_of_entity” is
port(all your input and output
signals);
end “name_of_entity”;
75. 8 – bit shifterarchitecture shifter1 of shift is
begin
reg : process(RST, CLK)
variable reg : bit_vector(0 to 7);
begin
if(RST = '1') then
reg := "00000000";
elsif(CLK = '1' and CLK'event)
then
if(LOAD = '1') then reg :=
Data;
. else
reg := reg(1 to 7) & reg(0);
end if;
end if;
Q <= reg;
end process;
end shifter1;
shifter1 is the name of my
architecture
shift is the name of my entity
reg is the name of my process
reg is also a local variable
Begin the process reg
if RST clear reg
else wait for a clock event then
reg = Data if LOAD signal is high
a bit shift
R gets the value of reg
end process
end architecture
76. TestBench for 8 bit
shifter
library ieee;
use ieee.std_logic_1164.all;
entity shift_testbench is
end shift_testbench;
architecture test of shift_testbench is
Signal CLK : bit;
signal RST : bit;
signal LOAD : bit;
signal Data :bit_vector(0 to 7);
signal Q :bit_vector(0 to 7);
still have to begin with entity
end the entity
test is the name of the
architecture
the signals have to be the
same as the port signals in
your entity declaration of
the program you want to
test.
77. TestBench for 8 bit Shifter
component shift is
port (CLK, RST, LOAD : in bit;
Data : in bit_vector(0 to 7);
Q : out bit_vector(0 to 7));
end component;
begin
test_shift: shift port map(
CLK => CLK ,
RST => RST,
LOAD => LOAD,
Data => Data,
Q => Q);
port has all the input and
output signals used in the
VHDL program
The port map is used to link the
signal Data from your VHDL
program to the signal Data in
your testbench
78. TestBench for 8 bit Shifter
clock_gen : process
begin
clk <= '0', '1' after 50 ns;
wait for 100 ns;
end process;
RST<='1', '0' after 200 ns;
test_process: process
begin
Data<="00000001";
LOAD<='1', '0' after 400 ns
wait;
end process;
end test;
creates a clock signal
this is a 10 MHz clock
end the process clock_gen
this is only done once to set it off
data is give a value
every 400 ns Data is reset to
“00000001”
end the process test_process
end the test
80. •PLD monitors data stream looking for commands
•PLD responds to On command by turning LED On
•PLD responds to Off command by turning LED Off
Functional Overview
On Off
“AB” “50”
