SlideShare a Scribd company logo
1 of 61
Processor Architecture And Interfacing
UNIT-1
Introduction to Assembly Language
Programming and 80386 Processors
Computer organization
How operational attributes are linked together and contribute to realize the
architectural specifications.
Deals with all physical components of computer systems that interacts with each other
to perform various functionalities.

Computer architecture
Decides architectural attributes of a hardware components needed to form a
relationship with other hardware component to form a functional system.
Computer architecture comes before computer organization
Architectural attributes - instruction set, word length, techniques for addressing
memories
Design and architecture of house - decides specifications
Organization - building the house by bricks or by latest technology
Software Abstraction
Hardware Abstraction
Hardware / Software Interface
Abstract CPU Architecture
Functional Blocks of a CPU
Central Hardware - A Microprocessor
A microprocessor -- also known as a CPU or central processing unit -- is a complete
computation engine that is fabricated on a single chip.

A microprocessor incorporates the functions of a computer's central processing unit
(CPU) on a single integrated circuit (IC) or at most a few integrated circuits

Three basic characteristics differentiate microprocessors:
•Instruction set: The set of instructions that the microprocessor can execute.
• bandwidth : The number of bits processed in a single instruction.
• clock speed : Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.
What’s difference between processors ?
What’s difference between INTEL processors ?
Development of Intel processor
(i) 8088
–
–
–

Has 16-bit registers and 8-bit data bus
20 bit address bus - address up to 1 MB of internal memory
Although registers can store up to 16-bits at a time but the data
bus is only able to transfer 8 bit data at one time

(ii) 8086
– Is similar to 8088 but has a 16-bit data bus and runs
faster.
–

20 bit address bus - address up to 1 MB of internal
memory
(iii) 80286
– Runs faster than 8086 and 8088
– Can address up to 16 MB of internal memory ( 24 bit address)
– multitasking => more than 1 task can be ran
simultaneously

(iv) 80386
– has 32-bit registers and 32-bit data bus
– can address up to 4 billion bytes. of memory (4 GB)
– support “virtual mode”, whereby it can swap portions of
memory onto disk: in this way, programs running concurrently
have space to operate.

(v) 80486
– has 32-bit registers and 32-bit data bus
– the presence of CACHE
(vi) Pentium
–
–
–
–

has 32-bit registers, 64-bit data bus
has separate caches for data and instruction
the processor can decode and execute more than one
instruction in one clock cycle (pipeline)

(vii) Pentium II & III
– has different paths to the cache and main memory
8086 Architecture
8086 Registers
8086 Architecture
Processor (CPU) is partitioned into two logical units:
1) An Execution Unit (EU)
2) A Bus Interface Unit (BIU)
EU
– EU is responsible for program execution
– Contains of an Arithmetic Logic Unit (ALU), a Control Unit (CU) and a number
of registers

BIU
– Delivers data and instructions to the EU.
– manage the bus control unit, segment registers and instruction queue.
– The BIU controls the buses that transfer the data to the EU, to memory and to
external input/output devices, whereas the segment registers control memory
addressing.
8086 Architecture

EU and BIU work in parallel, with the BIU keeping
one step ahead. The EU will notify the BIU when it
needs to data in memory or an I/O device or obtain
instruction from the BIU instruction queue.

When EU executes an instruction, BIU will fetch the
next instruction from the memory and insert it into
to instruction queue.
8086 Architecture
EU : Execution Unit
AX
BX
CX
DX

AH
BH
CH
DH

AL
BL
CL
DL
SP
BP
SI
DI

ALU
CU
Flag register

Instruction Pointer
(Program Counter)

BIU : Bus Interface Unit

Program Control
CS
DS
SS
ES

1
2
3
4

n

Bus
Control
Unit
Instruction
Queue

Bus
Addressing Data in Memory
•

•

•

Intel Personal Computer (PC) addresses its memory
according to bytes. (Every byte has a unique address
beginning with 0)
Depending on the model of a PC, CPU can access 1 or
more bytes at a time
Processor (CPU) keeps data in memory in reverse byte
sequence (reverse-byte sequence: low order byte in the low memory
address and high-order byte in the high memory address)
Example :

consider value 052916 (0529H)
2 bytes  05 and 29

register

05

29

29

05

memory

Address 04A2616
(low-order/least significant byte)

Address 04A2716
(high-order/most significant byte)

• When the processor takes data (a word or 2 bytes), it
will re-reverse the byte to its actual order 052916
Segment And Addressing
• Segments are special areas in the memory that is defined in a
program, containing the code, data, and stack.
• The segment position in the memory is not fixed and can not
be determined by the programmer
• 3 main segments for the programming process:
(i) Code Segment (CS)
• Contains the machine instructions that are to execute.
• Typically, the first executable instruction is at the start of this
segment, and the operating system links to that location to
begin program execution.
• CS register will hold the beginning address of this segment
(ii) Data Segment (DS)
• Contains program’s defined data, constants and working
areas.
• DS register is used to store the starting address of the DS
(iii) Stack Segment (SS)
• Contains any data or address that the program needs to
save temporarily or for used by your own “called”
subroutines.
• SS register is used to hold the starting address of this
segment
Stack segment
Contains the beginning
address of each segment

SS Register

Address

DS Register

Address

CS Register

Address

Data segment

Segment register
(in CPU)
Code segment

memory
(MM)
Stack segment

035F0

Data segment

02ED0

Code segment

01300

Contains the beginning
address of each segment

SS Register

035F

DS Register

02ED

CS Register

0130
Segment register
(in CPU)

memory
(MM)
Segment Offsets
• Within a program, all memory locations within a
segment are relative to the segment’s starting address.
• The distance in bytes from the segment address to
another location within the segment is expressed as an
offset (or displacement).
• Thus the first byte of the code segment is at offset
00, the second byte is at offset 01 and so forth.
• To reference any memory location in a segment (the
actual address), the processor combines the segment
address in a segment register with the offset value of
that location.  actual address = segment address + offset
Eg:
A starting address of data segment is 038E0, so the value in
DS register is 038E. An instruction references a location
with an offset of 0032H bytes from the start of the data
segment.
the actual address = DS segment address (0) + offset
= 038E(0) + 0032H
= 03912H
Ex. IF CS = 04F0

find physical address of data

(a) at an offset 3BE0

(b)

F3C8

in the code segment
Registers
• Registers are used to control instructions being
executed, to handle addressing of memory, and to
provide arithmetic capability
• Registers of Intel Processors can be categorized into:
1.
2.
3.
4.
5.

Segment register
Pointer register
General purpose register
Index register
Flag register
i) Segment register
There are 6 segment registers :
(a) CS register
• Contains the starting address of program’s code segment.
• The content of the CS register is added with the content in
the Instruction Pointer (IP) register to obtain the address
of the instruction that is to be fetched for execution.
(Note: common name for IP is PC (Program Counter))
(b) DS register
• Contains the starting address of a program’s data segment.
• The address in DS register will be added with the value in
the address field (in instruction format) to obtain the real
address of the data in data segment.
(c) SS Register
•
•

Contains the starting address of the stack segment.
The content in this register will be added with the
content in the Stack Pointer (SP) register to obtain the
required word.

(d) ES (Extra Segment) Register
•

•

Used by some string (character data) operations to
handle memory addressing
ES register is associated with the Data Index (DI)
register.

(e) FS and GS Registers
•

Additional extra segment registers introduced in
80386 for handling storage requirement.
(ii) Pointer Registers
•

There are 3 pointer registers in an Intel PC :

(a) Instruction Pointer register
• The 16-bit IP register contains the offset address
or displacement for the next instruction that will
be executed by the CPU
• The value in the IP register will be added into the
value in the CS register to obtain the real address
of an instruction
Example :
The content in CS register =
The content in IP register =
next instruction address:

39B40H
514H

39B40H
+
514H
.
3A054H
• Intel 80386 introduced 32-bit IP, known as EIP
(Extended IP)
(b) Stack Pointer Register (Stack Pointer (SP))
• The 16-bit SP register stores the displacement value that will be
combined with the value in the SS register to obtain the required
word in the stack
• Intel 80386 introduced 32-bit SP, known as ESP (Extended SP)
Example:
Value in register SS =
4BB30H
Value in register SP = + 412H
4BF42H

(c) Base Pointer Register
• The 16-bit BP register facilitates referencing parameters, which are data
and addresses that a program passes via a stack
• The processor combines the address in SS with the offset in BP
(iii) General Purpose Registers
There are 4 general-purpose registers, AX, BX, CX, DX:
(a) AX register
• Acts as the accumulator and is used in operations that involve input/output
and arithmetic
• The diagram below shows the AX register with the number of bits.
32 bits
8 bit

8 bit
AL

AH
AX
EAX

EAX
AX
AH
AL

: 32 bit
: 16 bit (rightmost 16-bit portion of EAX)
: 8 bit => leftmost 8 bits of AX (high portion)
: 8 bit => rightmost 8 bit of AX (low portion)
(b) BX Register
o Known as the base register since it is the only this general purpose
register that can be used as an index to extend addressing.
o This register also can be used for computations
o BX can also be combined with DI and SI register as a base registers for
special addressing like AX, BX is also consists of EBX, BH and BL

32 bits
8 bit

8 bit

BH

BL
BX

EBX
(c) CX Register
• known as count register
• may contain a value to control the number of times a loops is repeated or a value to shift bits
left or right
• CX can also be used for many computations
• Number of bits and fractions of the register is like below :
32 bits

8 bit

8 bit

CH

CL

CX

ECX
(d) DX Register
• Known as data register
• Some I/O operations require its use
• Multiply and divide operations that involve large values assume
the use of DX and AX together as a pair to hold the data or
result of operation.
• Number of bits and the fractions of the register is as below :

32 bits
8 bit

8 bit

DH

DL

DX
EDX
(iv) Index Register
There are 2 index registers, SI and DI
(a) SI Register
o Needed in operations that involve string (character) and is always
usually associated with the DS register
o SI : 16 bit
o ESI : 32 bit (80286 and above)
(b) DI Register
o Also used in operations that involve string (character) and it is
associated with the ES register
o DI : 16 bit
o EDI : 32 bit (80386 and above)
(v) FLAG Register
o Flags register contains bits that show the status of some activities
o Instructions that involve comparison and arithmetic will change the
flag status where some instruction will refer to the value of a specific bit
in the flag for next subsequent action
- 9 of its 16 bits indicate the current status of the computer
and the results of processing
- the above diagram shows the stated 9 bits

O

15

14

13

12

11

D

10

I

9

T

8

S

7

Z

6

A

5

4

3

P

2

1

C

0
O

15

14

13

12

11

D

10

I

9

T

8

S

7

Z

6

A

5

4

3

P

2

1

C

0

OF (overflow): indicate overflow of a high-order (leftmost) bit following arithmetic
DF (direction): Determines left or right direction for moving or comparing string
(character) data
IF (interrupt): indicates that all external interrupts such as keyboard entry are to be
processed or ignored
TF (trap): permits operation of the processor in single-step mode. Usually used in
“debugging” process
SF (sign): contains the resulting sign of an arithmetic operation (0 = +ve, 1 = -ve)
ZF (zero): indicates the result of an arithmetic or comparison operation (0 = non
zero; 1 = zero result)
AF (auxillary carry): contains a carry out of bit 3 into bit 4 in an arithmetic
operation, for specialized arithmetic
PF (parity): indicates the number of 1-bits that result from an operation. An even
number of bits causes so-called even parity and an odd number causes odd parity
CF (parity): contains carries from a high-order (leftmost) bit following an arithmetic
operation; also, contains the content of the last bit of a shift or rotate operation.
Introduction to assembly language programming
Levels of Programming Languages
1) Machine Language
– Consists of individual instructions that will be executed by the CPU one at
a time

2) Assembly Language (Low Level Language)
– Designed for a specific family of processors (different processor
groups/family has different Assembly Language)
– Consists of symbolic instructions directly related to machine language
instructions one-for-one and are assembled into machine language.

3) High Level Languages
– e.g. : C, C++ and Vbasic
– Designed to eliminate the technicalities of a particular computer.
– Statements compiled in a high level language typically generate many lowlevel instructions.
Reasons for using Assembly Language
1. A program written in Assembly Language requires
considerably less memory and execution time than one
written in a high –level language.
2. Assembly Language gives a programmer the ability to
perform highly technical tasks that would be difficult, if
not impossible in a high-level language.
3. Although most software specialists develop new
applications in high-level languages, which are easier to
write and maintain, a common practice is to recode in
assembly language those sections that are time-critical.
4. Resident programs (that reside in memory while other
program execute) and interrupt service routines (that
handle input and output) are almost always develop in
Assembly Language.
Assembly Language
• Program implemented directly on the physical CPU
• Is not portable between various families of processors
• It gives programmers the insight required to write effective code in high-level
Basic
• Every computer - has at its heart exactly two things: a CPU and some memory
• Computer program is nothing more than a collection of binary codes in memory.
• Different numbers tell the CPU to do different things.
• The CPU reads the op-code one at a time, decodes them, and does what the
numbers say.
64
opcode 64 - means add 1 to AX.
8E
opcode 8E- swap numbers stored in AX with BX.
• 184, 0, 184, 142, 216, 198, 6, 158, 15, 36, 205, 32. ( Display $ )
Assembly Language
• Op codes are not understood by human.
• Programs could be written using words instead of numbers is assembly language
• A special program called an assembler would then take the programmer's words

and convert them to numbers that the computer could understand.
The program above, written in assembly language, looks like this:
MOV AX, 47104
MOV DS, AX
MOV [3998], 36
INT 32
• Assembler converts each line of code into CPU-level instruction
• INT instruction transfers processor control to the device drivers
or operating system.
Assembly Language
• Registers used to store numbers
• DS happens to be a segment register and is used to pick which area of memory the
CPU can write to
• In our program, we put the number 47104 into DS, which tells the CPU to access the
memory on the video card.
• Put the number 36 ($) into location 3998 of the video card's memory
• 3998 is the memory location of the bottom right hand corner of the screen, a dollar
sign shows up on the screen a few microseconds later.
• An interrupt is used to stop one program and execute another in its place.
• In our case, we want interrupt 32, which ends our program and goes back to MSDOS, or whatever other program was used to start our program
Assembly Language
• Running the Program
• Next, click on your start menu, and run the program called MS-DOS Prompt
• Type DEBUG and press enter
• You will see the Debug prompt, which is a simple dash.
• We are now in a program called Debug. Debug is a powerful utility that lets you
directly access the registers and memory of your computer for various purposes.
• Debug's a command is for assemble.
• You will see something like 1073:0100.
• This is the memory location we are going to enter assembly language
instructions at.
• The first number is the segment, and the second number is the memory
location within the segment (offset)
• Debug only understands hexadecimal numbers,
• Enter our program now. Type each of the instructions - when you finish entering the
last instruction, press enter twice
mov ax,B800
movds,ax
mov byte[0F9E],24
int 20
Assembly Language
• Once you have entered the program, you can go ahead and run it.
• Simply type g for go and press enter when you are ready to start the program.

• You should see a dollar sign in the lower right hand corner of your screen
• These words are put out by Debug to let you know that the program ended normally
• Go ahead and type q to get out of Debug
• Now, type exit to get out of MS-DOS. You should now be back in Windows
Assembly Language Program Development Steps
1. Analyze the problem
2. Create source program ----------- Use Editor ---------- test.asm
3. Assemble the source file ----- Use Assembler ------

test.obj , test.lst

4. Link the object file ---- Use Linker ----- test.exe , test. Map
5. Run the program independently or use Debugger / Emulator
Assembly Language Program Development Tools
• Editor
• Assembler

• Linker
• Loader

• Debugger
• Emulator
Editor
•Is a program that helps to create and modify contents of a file
•We can write assembly language instructions or mnemonics and store them

as a file with extension .ASM
.data
msg db
.code
mov
mov
mov
mov
int

"Hello, World!", 0Dh,0Ah, 24h

ax,@data
ds,ax
dx, offset msg
ah, 09h
21h

mov ah, 0
int 16h

Hello.asm
The Assembler
• Translates the mnemonics into binary machine code
• WE will use TASM or MASM

- Finds displacement (offset) of data and labels and puts this into symbol table
- Inserts these offsets into the translated binary code
- Pseudo Instructions are special commands to the assembler about the positioning of
the program, the address the program should presumed to be assembled at,
Command :

TASM /l hello.asm
Hello.lst file
-- Produces binary codes for the combined module.
-- Also produces a map file having addresses of all linked files
-- Linker does not assign absolute address -- only relative address from 0000
hence the program is relocatable code
Debugger
The Assembly Language Debugger is a tool for debugging executable programs at
the assembly level.
Debugger loads the object code into system memory (RAM)
Execute and debug the program
Features
- Step into / Step over - to see register and memory contents
- Breakpoints
- Easy memory manipulation
- Disassembler for intel x86 instructions
- Easy register manipulation
Debugger
The Assembly Language Debugger is a tool for debugging executable programs at
the assembly level.
Debugger loads the object code into system memory (RAM)
Execute and debug the program
Features
- Step into / Step over - to see register and memory contents
- Breakpoints
- Easy memory manipulation
- Disassembler for intel x86 instructions
- Easy register manipulation
Emulator
• emulator is hardware or software or both that duplicates (or emulates) the functions
of one computer system (the guest) in another computer system (the host)
• emulated behavior closely resembles the behavior of the real system (the guest)
• exact reproduction of behavior as against simulation
• Used to test and debug hardware of an external system
• Host is connected to guest by cable
• Then the object code is downloaded into the guest’s memory for execution
• All features of debugger are present in the emulator
• The only difference is that emulator gets the status of all memory locations

and registers from the external hardware.
• This traced data can be analyzed to find errors

More Related Content

What's hot

Micro[processor
Micro[processorMicro[processor
Micro[processorcollege
 
8086 Microprocessor
8086 Microprocessor 8086 Microprocessor
8086 Microprocessor Vijay Kumar
 
Addressing modes (detailed data path)
Addressing modes (detailed data path)Addressing modes (detailed data path)
Addressing modes (detailed data path)Mahesh Kumar Attri
 
8086 microprocessor introduction
8086 microprocessor introduction8086 microprocessor introduction
8086 microprocessor introductionAakash Ugale
 
Introduction to 8086 microprocessor
Introduction to 8086 microprocessorIntroduction to 8086 microprocessor
Introduction to 8086 microprocessorShreyans Pathak
 
Chapter 2 The 8088 Microprocessor
Chapter 2   The 8088 MicroprocessorChapter 2   The 8088 Microprocessor
Chapter 2 The 8088 MicroprocessorDwight Sabio
 
8086 architecture and pin description
8086 architecture and pin description 8086 architecture and pin description
8086 architecture and pin description Aswini Dharmaraj
 
INTERNAL STRUCTURE OF 8086 MICROPROCESSOR
INTERNAL STRUCTURE OF  8086 MICROPROCESSORINTERNAL STRUCTURE OF  8086 MICROPROCESSOR
INTERNAL STRUCTURE OF 8086 MICROPROCESSORMd. Hasnat Shoheb
 
Intel 8086 microprocessor
Intel 8086 microprocessorIntel 8086 microprocessor
Intel 8086 microprocessorRavi Yasas
 

What's hot (20)

8086 micro processor
8086 micro processor8086 micro processor
8086 micro processor
 
Micro[processor
Micro[processorMicro[processor
Micro[processor
 
Intel 8086
Intel 8086 Intel 8086
Intel 8086
 
Mpi chapter 2
Mpi chapter 2Mpi chapter 2
Mpi chapter 2
 
8086 architecture By Er. Swapnil Kaware
8086 architecture By Er. Swapnil Kaware8086 architecture By Er. Swapnil Kaware
8086 architecture By Er. Swapnil Kaware
 
Register & Memory
Register & MemoryRegister & Memory
Register & Memory
 
8086 architecture
8086 architecture8086 architecture
8086 architecture
 
8086 Microprocessor
8086 Microprocessor 8086 Microprocessor
8086 Microprocessor
 
intel 8086 introduction
intel 8086 introductionintel 8086 introduction
intel 8086 introduction
 
MPMC Unit-1
MPMC Unit-1MPMC Unit-1
MPMC Unit-1
 
Addressing modes (detailed data path)
Addressing modes (detailed data path)Addressing modes (detailed data path)
Addressing modes (detailed data path)
 
8086
8086 8086
8086
 
8086 microprocessor introduction
8086 microprocessor introduction8086 microprocessor introduction
8086 microprocessor introduction
 
Introduction to 8086 microprocessor
Introduction to 8086 microprocessorIntroduction to 8086 microprocessor
Introduction to 8086 microprocessor
 
Chapter 2 The 8088 Microprocessor
Chapter 2   The 8088 MicroprocessorChapter 2   The 8088 Microprocessor
Chapter 2 The 8088 Microprocessor
 
8086 architecture and pin description
8086 architecture and pin description 8086 architecture and pin description
8086 architecture and pin description
 
INTERNAL STRUCTURE OF 8086 MICROPROCESSOR
INTERNAL STRUCTURE OF  8086 MICROPROCESSORINTERNAL STRUCTURE OF  8086 MICROPROCESSOR
INTERNAL STRUCTURE OF 8086 MICROPROCESSOR
 
Intel 8086 microprocessor
Intel 8086 microprocessorIntel 8086 microprocessor
Intel 8086 microprocessor
 
Cs14 406 mod1
Cs14 406 mod1Cs14 406 mod1
Cs14 406 mod1
 
Amp
AmpAmp
Amp
 

Similar to Processor Architecture And Interfacing: Understanding Intel Processors and 80386 Architecture

8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd yearBharghavteja1
 
Presentation on 8086 microprocessor
Presentation on 8086 microprocessorPresentation on 8086 microprocessor
Presentation on 8086 microprocessorDiponkor Bala
 
The Intel 8086 microprocessor
The Intel 8086 microprocessorThe Intel 8086 microprocessor
The Intel 8086 microprocessorGeorge Thomas
 
Assembly_Language _Programming_UNIT.pptx
Assembly_Language _Programming_UNIT.pptxAssembly_Language _Programming_UNIT.pptx
Assembly_Language _Programming_UNIT.pptxVickyThakur61
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formatsMazin Alwaaly
 
3 organization of intel 8086
3 organization of intel 80863 organization of intel 8086
3 organization of intel 8086ELIMENG
 
Introduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorIntroduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorDarling Jemima
 
Presentation on 8086 Microprocessor
Presentation  on   8086 MicroprocessorPresentation  on   8086 Microprocessor
Presentation on 8086 MicroprocessorNahian Ahmed
 
the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1Basel Mansour
 
8086_architecture MMC PPT.ppt
8086_architecture MMC PPT.ppt8086_architecture MMC PPT.ppt
8086_architecture MMC PPT.pptJamesAlpha3
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01jemimajerome
 

Similar to Processor Architecture And Interfacing: Understanding Intel Processors and 80386 Architecture (20)

Microprocessor
MicroprocessorMicroprocessor
Microprocessor
 
U I - 4. 80386 Real mode.pptx
U I - 4. 80386 Real mode.pptxU I - 4. 80386 Real mode.pptx
U I - 4. 80386 Real mode.pptx
 
8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year8086 microprocessor pptx JNTUH ece 3rd year
8086 microprocessor pptx JNTUH ece 3rd year
 
Presentation on 8086 microprocessor
Presentation on 8086 microprocessorPresentation on 8086 microprocessor
Presentation on 8086 microprocessor
 
8086 Architecture
8086 Architecture8086 Architecture
8086 Architecture
 
The Intel 8086 microprocessor
The Intel 8086 microprocessorThe Intel 8086 microprocessor
The Intel 8086 microprocessor
 
microprocessor
 microprocessor microprocessor
microprocessor
 
Assembly_Language _Programming_UNIT.pptx
Assembly_Language _Programming_UNIT.pptxAssembly_Language _Programming_UNIT.pptx
Assembly_Language _Programming_UNIT.pptx
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formats
 
3 organization of intel 8086
3 organization of intel 80863 organization of intel 8086
3 organization of intel 8086
 
Introduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorIntroduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM Processor
 
Presentation on 8086 Microprocessor
Presentation  on   8086 MicroprocessorPresentation  on   8086 Microprocessor
Presentation on 8086 Microprocessor
 
the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1
 
8086_architecture MMC PPT.ppt
8086_architecture MMC PPT.ppt8086_architecture MMC PPT.ppt
8086_architecture MMC PPT.ppt
 
Details 8086 Microprocessor
Details 8086 MicroprocessorDetails 8086 Microprocessor
Details 8086 Microprocessor
 
8086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp018086 microprocessor-architecture-120207111857-phpapp01
8086 microprocessor-architecture-120207111857-phpapp01
 
8086 archi notes final
8086 archi notes final8086 archi notes final
8086 archi notes final
 
8086 archi notes final
8086 archi notes final8086 archi notes final
8086 archi notes final
 
Cao 2012
Cao 2012Cao 2012
Cao 2012
 
COA_UNIT_I.pptx
COA_UNIT_I.pptxCOA_UNIT_I.pptx
COA_UNIT_I.pptx
 

Recently uploaded

My INSURER PTE LTD - Insurtech Innovation Award 2024
My INSURER PTE LTD - Insurtech Innovation Award 2024My INSURER PTE LTD - Insurtech Innovation Award 2024
My INSURER PTE LTD - Insurtech Innovation Award 2024The Digital Insurer
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Scott Keck-Warren
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 3652toLead Limited
 
"Debugging python applications inside k8s environment", Andrii Soldatenko
"Debugging python applications inside k8s environment", Andrii Soldatenko"Debugging python applications inside k8s environment", Andrii Soldatenko
"Debugging python applications inside k8s environment", Andrii SoldatenkoFwdays
 
Are Multi-Cloud and Serverless Good or Bad?
Are Multi-Cloud and Serverless Good or Bad?Are Multi-Cloud and Serverless Good or Bad?
Are Multi-Cloud and Serverless Good or Bad?Mattias Andersson
 
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024BookNet Canada
 
My Hashitalk Indonesia April 2024 Presentation
My Hashitalk Indonesia April 2024 PresentationMy Hashitalk Indonesia April 2024 Presentation
My Hashitalk Indonesia April 2024 PresentationRidwan Fadjar
 
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)Bun (KitWorks Team Study 노별마루 발표 2024.4.22)
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)Wonjun Hwang
 
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostLeverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostZilliz
 
Beyond Boundaries: Leveraging No-Code Solutions for Industry Innovation
Beyond Boundaries: Leveraging No-Code Solutions for Industry InnovationBeyond Boundaries: Leveraging No-Code Solutions for Industry Innovation
Beyond Boundaries: Leveraging No-Code Solutions for Industry InnovationSafe Software
 
"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr BaganFwdays
 
Artificial intelligence in cctv survelliance.pptx
Artificial intelligence in cctv survelliance.pptxArtificial intelligence in cctv survelliance.pptx
Artificial intelligence in cctv survelliance.pptxhariprasad279825
 
Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Manik S Magar
 
WordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your BrandWordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your Brandgvaughan
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationSlibray Presentation
 
Install Stable Diffusion in windows machine
Install Stable Diffusion in windows machineInstall Stable Diffusion in windows machine
Install Stable Diffusion in windows machinePadma Pradeep
 
Unraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfUnraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfAlex Barbosa Coqueiro
 
The Future of Software Development - Devin AI Innovative Approach.pdf
The Future of Software Development - Devin AI Innovative Approach.pdfThe Future of Software Development - Devin AI Innovative Approach.pdf
The Future of Software Development - Devin AI Innovative Approach.pdfSeasiaInfotech2
 

Recently uploaded (20)

My INSURER PTE LTD - Insurtech Innovation Award 2024
My INSURER PTE LTD - Insurtech Innovation Award 2024My INSURER PTE LTD - Insurtech Innovation Award 2024
My INSURER PTE LTD - Insurtech Innovation Award 2024
 
Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024Advanced Test Driven-Development @ php[tek] 2024
Advanced Test Driven-Development @ php[tek] 2024
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365
 
"Debugging python applications inside k8s environment", Andrii Soldatenko
"Debugging python applications inside k8s environment", Andrii Soldatenko"Debugging python applications inside k8s environment", Andrii Soldatenko
"Debugging python applications inside k8s environment", Andrii Soldatenko
 
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptxE-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
E-Vehicle_Hacking_by_Parul Sharma_null_owasp.pptx
 
Are Multi-Cloud and Serverless Good or Bad?
Are Multi-Cloud and Serverless Good or Bad?Are Multi-Cloud and Serverless Good or Bad?
Are Multi-Cloud and Serverless Good or Bad?
 
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
New from BookNet Canada for 2024: BNC CataList - Tech Forum 2024
 
My Hashitalk Indonesia April 2024 Presentation
My Hashitalk Indonesia April 2024 PresentationMy Hashitalk Indonesia April 2024 Presentation
My Hashitalk Indonesia April 2024 Presentation
 
DMCC Future of Trade Web3 - Special Edition
DMCC Future of Trade Web3 - Special EditionDMCC Future of Trade Web3 - Special Edition
DMCC Future of Trade Web3 - Special Edition
 
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)Bun (KitWorks Team Study 노별마루 발표 2024.4.22)
Bun (KitWorks Team Study 노별마루 발표 2024.4.22)
 
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage CostLeverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
Leverage Zilliz Serverless - Up to 50X Saving for Your Vector Storage Cost
 
Beyond Boundaries: Leveraging No-Code Solutions for Industry Innovation
Beyond Boundaries: Leveraging No-Code Solutions for Industry InnovationBeyond Boundaries: Leveraging No-Code Solutions for Industry Innovation
Beyond Boundaries: Leveraging No-Code Solutions for Industry Innovation
 
"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan"ML in Production",Oleksandr Bagan
"ML in Production",Oleksandr Bagan
 
Artificial intelligence in cctv survelliance.pptx
Artificial intelligence in cctv survelliance.pptxArtificial intelligence in cctv survelliance.pptx
Artificial intelligence in cctv survelliance.pptx
 
Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!Anypoint Exchange: It’s Not Just a Repo!
Anypoint Exchange: It’s Not Just a Repo!
 
WordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your BrandWordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your Brand
 
Connect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck PresentationConnect Wave/ connectwave Pitch Deck Presentation
Connect Wave/ connectwave Pitch Deck Presentation
 
Install Stable Diffusion in windows machine
Install Stable Diffusion in windows machineInstall Stable Diffusion in windows machine
Install Stable Diffusion in windows machine
 
Unraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfUnraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdf
 
The Future of Software Development - Devin AI Innovative Approach.pdf
The Future of Software Development - Devin AI Innovative Approach.pdfThe Future of Software Development - Devin AI Innovative Approach.pdf
The Future of Software Development - Devin AI Innovative Approach.pdf
 

Processor Architecture And Interfacing: Understanding Intel Processors and 80386 Architecture

  • 2. UNIT-1 Introduction to Assembly Language Programming and 80386 Processors
  • 3. Computer organization How operational attributes are linked together and contribute to realize the architectural specifications. Deals with all physical components of computer systems that interacts with each other to perform various functionalities. Computer architecture Decides architectural attributes of a hardware components needed to form a relationship with other hardware component to form a functional system. Computer architecture comes before computer organization Architectural attributes - instruction set, word length, techniques for addressing memories Design and architecture of house - decides specifications Organization - building the house by bricks or by latest technology
  • 4.
  • 7.
  • 11. Central Hardware - A Microprocessor A microprocessor -- also known as a CPU or central processing unit -- is a complete computation engine that is fabricated on a single chip. A microprocessor incorporates the functions of a computer's central processing unit (CPU) on a single integrated circuit (IC) or at most a few integrated circuits Three basic characteristics differentiate microprocessors: •Instruction set: The set of instructions that the microprocessor can execute. • bandwidth : The number of bits processed in a single instruction. • clock speed : Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.
  • 13. What’s difference between INTEL processors ? Development of Intel processor (i) 8088 – – – Has 16-bit registers and 8-bit data bus 20 bit address bus - address up to 1 MB of internal memory Although registers can store up to 16-bits at a time but the data bus is only able to transfer 8 bit data at one time (ii) 8086 – Is similar to 8088 but has a 16-bit data bus and runs faster. – 20 bit address bus - address up to 1 MB of internal memory
  • 14. (iii) 80286 – Runs faster than 8086 and 8088 – Can address up to 16 MB of internal memory ( 24 bit address) – multitasking => more than 1 task can be ran simultaneously (iv) 80386 – has 32-bit registers and 32-bit data bus – can address up to 4 billion bytes. of memory (4 GB) – support “virtual mode”, whereby it can swap portions of memory onto disk: in this way, programs running concurrently have space to operate. (v) 80486 – has 32-bit registers and 32-bit data bus – the presence of CACHE
  • 15. (vi) Pentium – – – – has 32-bit registers, 64-bit data bus has separate caches for data and instruction the processor can decode and execute more than one instruction in one clock cycle (pipeline) (vii) Pentium II & III – has different paths to the cache and main memory
  • 18.
  • 19. 8086 Architecture Processor (CPU) is partitioned into two logical units: 1) An Execution Unit (EU) 2) A Bus Interface Unit (BIU) EU – EU is responsible for program execution – Contains of an Arithmetic Logic Unit (ALU), a Control Unit (CU) and a number of registers BIU – Delivers data and instructions to the EU. – manage the bus control unit, segment registers and instruction queue. – The BIU controls the buses that transfer the data to the EU, to memory and to external input/output devices, whereas the segment registers control memory addressing.
  • 20. 8086 Architecture EU and BIU work in parallel, with the BIU keeping one step ahead. The EU will notify the BIU when it needs to data in memory or an I/O device or obtain instruction from the BIU instruction queue. When EU executes an instruction, BIU will fetch the next instruction from the memory and insert it into to instruction queue.
  • 21. 8086 Architecture EU : Execution Unit AX BX CX DX AH BH CH DH AL BL CL DL SP BP SI DI ALU CU Flag register Instruction Pointer (Program Counter) BIU : Bus Interface Unit Program Control CS DS SS ES 1 2 3 4 n Bus Control Unit Instruction Queue Bus
  • 22. Addressing Data in Memory • • • Intel Personal Computer (PC) addresses its memory according to bytes. (Every byte has a unique address beginning with 0) Depending on the model of a PC, CPU can access 1 or more bytes at a time Processor (CPU) keeps data in memory in reverse byte sequence (reverse-byte sequence: low order byte in the low memory address and high-order byte in the high memory address)
  • 23. Example : consider value 052916 (0529H) 2 bytes  05 and 29 register 05 29 29 05 memory Address 04A2616 (low-order/least significant byte) Address 04A2716 (high-order/most significant byte) • When the processor takes data (a word or 2 bytes), it will re-reverse the byte to its actual order 052916
  • 24. Segment And Addressing • Segments are special areas in the memory that is defined in a program, containing the code, data, and stack. • The segment position in the memory is not fixed and can not be determined by the programmer • 3 main segments for the programming process: (i) Code Segment (CS) • Contains the machine instructions that are to execute. • Typically, the first executable instruction is at the start of this segment, and the operating system links to that location to begin program execution. • CS register will hold the beginning address of this segment
  • 25. (ii) Data Segment (DS) • Contains program’s defined data, constants and working areas. • DS register is used to store the starting address of the DS (iii) Stack Segment (SS) • Contains any data or address that the program needs to save temporarily or for used by your own “called” subroutines. • SS register is used to hold the starting address of this segment
  • 26. Stack segment Contains the beginning address of each segment SS Register Address DS Register Address CS Register Address Data segment Segment register (in CPU) Code segment memory (MM)
  • 27. Stack segment 035F0 Data segment 02ED0 Code segment 01300 Contains the beginning address of each segment SS Register 035F DS Register 02ED CS Register 0130 Segment register (in CPU) memory (MM)
  • 28. Segment Offsets • Within a program, all memory locations within a segment are relative to the segment’s starting address. • The distance in bytes from the segment address to another location within the segment is expressed as an offset (or displacement). • Thus the first byte of the code segment is at offset 00, the second byte is at offset 01 and so forth. • To reference any memory location in a segment (the actual address), the processor combines the segment address in a segment register with the offset value of that location.  actual address = segment address + offset
  • 29. Eg: A starting address of data segment is 038E0, so the value in DS register is 038E. An instruction references a location with an offset of 0032H bytes from the start of the data segment. the actual address = DS segment address (0) + offset = 038E(0) + 0032H = 03912H Ex. IF CS = 04F0 find physical address of data (a) at an offset 3BE0 (b) F3C8 in the code segment
  • 30. Registers • Registers are used to control instructions being executed, to handle addressing of memory, and to provide arithmetic capability • Registers of Intel Processors can be categorized into: 1. 2. 3. 4. 5. Segment register Pointer register General purpose register Index register Flag register
  • 31. i) Segment register There are 6 segment registers : (a) CS register • Contains the starting address of program’s code segment. • The content of the CS register is added with the content in the Instruction Pointer (IP) register to obtain the address of the instruction that is to be fetched for execution. (Note: common name for IP is PC (Program Counter)) (b) DS register • Contains the starting address of a program’s data segment. • The address in DS register will be added with the value in the address field (in instruction format) to obtain the real address of the data in data segment.
  • 32. (c) SS Register • • Contains the starting address of the stack segment. The content in this register will be added with the content in the Stack Pointer (SP) register to obtain the required word. (d) ES (Extra Segment) Register • • Used by some string (character data) operations to handle memory addressing ES register is associated with the Data Index (DI) register. (e) FS and GS Registers • Additional extra segment registers introduced in 80386 for handling storage requirement.
  • 33. (ii) Pointer Registers • There are 3 pointer registers in an Intel PC : (a) Instruction Pointer register • The 16-bit IP register contains the offset address or displacement for the next instruction that will be executed by the CPU • The value in the IP register will be added into the value in the CS register to obtain the real address of an instruction
  • 34. Example : The content in CS register = The content in IP register = next instruction address: 39B40H 514H 39B40H + 514H . 3A054H • Intel 80386 introduced 32-bit IP, known as EIP (Extended IP)
  • 35. (b) Stack Pointer Register (Stack Pointer (SP)) • The 16-bit SP register stores the displacement value that will be combined with the value in the SS register to obtain the required word in the stack • Intel 80386 introduced 32-bit SP, known as ESP (Extended SP) Example: Value in register SS = 4BB30H Value in register SP = + 412H 4BF42H (c) Base Pointer Register • The 16-bit BP register facilitates referencing parameters, which are data and addresses that a program passes via a stack • The processor combines the address in SS with the offset in BP
  • 36. (iii) General Purpose Registers There are 4 general-purpose registers, AX, BX, CX, DX: (a) AX register • Acts as the accumulator and is used in operations that involve input/output and arithmetic • The diagram below shows the AX register with the number of bits. 32 bits 8 bit 8 bit AL AH AX EAX EAX AX AH AL : 32 bit : 16 bit (rightmost 16-bit portion of EAX) : 8 bit => leftmost 8 bits of AX (high portion) : 8 bit => rightmost 8 bit of AX (low portion)
  • 37. (b) BX Register o Known as the base register since it is the only this general purpose register that can be used as an index to extend addressing. o This register also can be used for computations o BX can also be combined with DI and SI register as a base registers for special addressing like AX, BX is also consists of EBX, BH and BL 32 bits 8 bit 8 bit BH BL BX EBX
  • 38. (c) CX Register • known as count register • may contain a value to control the number of times a loops is repeated or a value to shift bits left or right • CX can also be used for many computations • Number of bits and fractions of the register is like below : 32 bits 8 bit 8 bit CH CL CX ECX
  • 39. (d) DX Register • Known as data register • Some I/O operations require its use • Multiply and divide operations that involve large values assume the use of DX and AX together as a pair to hold the data or result of operation. • Number of bits and the fractions of the register is as below : 32 bits 8 bit 8 bit DH DL DX EDX
  • 40. (iv) Index Register There are 2 index registers, SI and DI (a) SI Register o Needed in operations that involve string (character) and is always usually associated with the DS register o SI : 16 bit o ESI : 32 bit (80286 and above) (b) DI Register o Also used in operations that involve string (character) and it is associated with the ES register o DI : 16 bit o EDI : 32 bit (80386 and above)
  • 41. (v) FLAG Register o Flags register contains bits that show the status of some activities o Instructions that involve comparison and arithmetic will change the flag status where some instruction will refer to the value of a specific bit in the flag for next subsequent action - 9 of its 16 bits indicate the current status of the computer and the results of processing - the above diagram shows the stated 9 bits O 15 14 13 12 11 D 10 I 9 T 8 S 7 Z 6 A 5 4 3 P 2 1 C 0
  • 42. O 15 14 13 12 11 D 10 I 9 T 8 S 7 Z 6 A 5 4 3 P 2 1 C 0 OF (overflow): indicate overflow of a high-order (leftmost) bit following arithmetic DF (direction): Determines left or right direction for moving or comparing string (character) data IF (interrupt): indicates that all external interrupts such as keyboard entry are to be processed or ignored TF (trap): permits operation of the processor in single-step mode. Usually used in “debugging” process SF (sign): contains the resulting sign of an arithmetic operation (0 = +ve, 1 = -ve) ZF (zero): indicates the result of an arithmetic or comparison operation (0 = non zero; 1 = zero result) AF (auxillary carry): contains a carry out of bit 3 into bit 4 in an arithmetic operation, for specialized arithmetic PF (parity): indicates the number of 1-bits that result from an operation. An even number of bits causes so-called even parity and an odd number causes odd parity CF (parity): contains carries from a high-order (leftmost) bit following an arithmetic operation; also, contains the content of the last bit of a shift or rotate operation.
  • 43. Introduction to assembly language programming Levels of Programming Languages 1) Machine Language – Consists of individual instructions that will be executed by the CPU one at a time 2) Assembly Language (Low Level Language) – Designed for a specific family of processors (different processor groups/family has different Assembly Language) – Consists of symbolic instructions directly related to machine language instructions one-for-one and are assembled into machine language. 3) High Level Languages – e.g. : C, C++ and Vbasic – Designed to eliminate the technicalities of a particular computer. – Statements compiled in a high level language typically generate many lowlevel instructions.
  • 44. Reasons for using Assembly Language 1. A program written in Assembly Language requires considerably less memory and execution time than one written in a high –level language. 2. Assembly Language gives a programmer the ability to perform highly technical tasks that would be difficult, if not impossible in a high-level language. 3. Although most software specialists develop new applications in high-level languages, which are easier to write and maintain, a common practice is to recode in assembly language those sections that are time-critical. 4. Resident programs (that reside in memory while other program execute) and interrupt service routines (that handle input and output) are almost always develop in Assembly Language.
  • 45. Assembly Language • Program implemented directly on the physical CPU • Is not portable between various families of processors • It gives programmers the insight required to write effective code in high-level Basic • Every computer - has at its heart exactly two things: a CPU and some memory • Computer program is nothing more than a collection of binary codes in memory. • Different numbers tell the CPU to do different things. • The CPU reads the op-code one at a time, decodes them, and does what the numbers say. 64 opcode 64 - means add 1 to AX. 8E opcode 8E- swap numbers stored in AX with BX. • 184, 0, 184, 142, 216, 198, 6, 158, 15, 36, 205, 32. ( Display $ )
  • 46. Assembly Language • Op codes are not understood by human. • Programs could be written using words instead of numbers is assembly language • A special program called an assembler would then take the programmer's words and convert them to numbers that the computer could understand. The program above, written in assembly language, looks like this: MOV AX, 47104 MOV DS, AX MOV [3998], 36 INT 32 • Assembler converts each line of code into CPU-level instruction • INT instruction transfers processor control to the device drivers or operating system.
  • 47. Assembly Language • Registers used to store numbers • DS happens to be a segment register and is used to pick which area of memory the CPU can write to • In our program, we put the number 47104 into DS, which tells the CPU to access the memory on the video card. • Put the number 36 ($) into location 3998 of the video card's memory • 3998 is the memory location of the bottom right hand corner of the screen, a dollar sign shows up on the screen a few microseconds later. • An interrupt is used to stop one program and execute another in its place. • In our case, we want interrupt 32, which ends our program and goes back to MSDOS, or whatever other program was used to start our program
  • 48. Assembly Language • Running the Program • Next, click on your start menu, and run the program called MS-DOS Prompt • Type DEBUG and press enter • You will see the Debug prompt, which is a simple dash. • We are now in a program called Debug. Debug is a powerful utility that lets you directly access the registers and memory of your computer for various purposes. • Debug's a command is for assemble. • You will see something like 1073:0100. • This is the memory location we are going to enter assembly language instructions at. • The first number is the segment, and the second number is the memory location within the segment (offset) • Debug only understands hexadecimal numbers, • Enter our program now. Type each of the instructions - when you finish entering the last instruction, press enter twice mov ax,B800 movds,ax mov byte[0F9E],24 int 20
  • 49. Assembly Language • Once you have entered the program, you can go ahead and run it. • Simply type g for go and press enter when you are ready to start the program. • You should see a dollar sign in the lower right hand corner of your screen • These words are put out by Debug to let you know that the program ended normally • Go ahead and type q to get out of Debug • Now, type exit to get out of MS-DOS. You should now be back in Windows
  • 50.
  • 51. Assembly Language Program Development Steps 1. Analyze the problem 2. Create source program ----------- Use Editor ---------- test.asm 3. Assemble the source file ----- Use Assembler ------ test.obj , test.lst 4. Link the object file ---- Use Linker ----- test.exe , test. Map 5. Run the program independently or use Debugger / Emulator
  • 52. Assembly Language Program Development Tools • Editor • Assembler • Linker • Loader • Debugger • Emulator
  • 53. Editor •Is a program that helps to create and modify contents of a file •We can write assembly language instructions or mnemonics and store them as a file with extension .ASM .data msg db .code mov mov mov mov int "Hello, World!", 0Dh,0Ah, 24h ax,@data ds,ax dx, offset msg ah, 09h 21h mov ah, 0 int 16h Hello.asm
  • 54. The Assembler • Translates the mnemonics into binary machine code • WE will use TASM or MASM - Finds displacement (offset) of data and labels and puts this into symbol table - Inserts these offsets into the translated binary code - Pseudo Instructions are special commands to the assembler about the positioning of the program, the address the program should presumed to be assembled at, Command : TASM /l hello.asm
  • 56. -- Produces binary codes for the combined module. -- Also produces a map file having addresses of all linked files -- Linker does not assign absolute address -- only relative address from 0000 hence the program is relocatable code
  • 57.
  • 58.
  • 59. Debugger The Assembly Language Debugger is a tool for debugging executable programs at the assembly level. Debugger loads the object code into system memory (RAM) Execute and debug the program Features - Step into / Step over - to see register and memory contents - Breakpoints - Easy memory manipulation - Disassembler for intel x86 instructions - Easy register manipulation
  • 60. Debugger The Assembly Language Debugger is a tool for debugging executable programs at the assembly level. Debugger loads the object code into system memory (RAM) Execute and debug the program Features - Step into / Step over - to see register and memory contents - Breakpoints - Easy memory manipulation - Disassembler for intel x86 instructions - Easy register manipulation
  • 61. Emulator • emulator is hardware or software or both that duplicates (or emulates) the functions of one computer system (the guest) in another computer system (the host) • emulated behavior closely resembles the behavior of the real system (the guest) • exact reproduction of behavior as against simulation • Used to test and debug hardware of an external system • Host is connected to guest by cable • Then the object code is downloaded into the guest’s memory for execution • All features of debugger are present in the emulator • The only difference is that emulator gets the status of all memory locations and registers from the external hardware. • This traced data can be analyzed to find errors