This slide summarizes the steps of modeling a new processor instruction set architecture (ISA)

1. Compiled program
with target toolchain
Target binary
0101…111
Emulation on existing
platform (e.g., x86)
Equivalent
instructions
(translation)
Input (e.g, Image)
OutputEMULATION
Instruction Set
Simulator (ISS)
OutputISS
Architectural
Simulator
OutputARCH_SIM OutputGROUND_TRUTH
Impl. on mature
platform (e.g., x86)
= = =
e.g., Vector add -> for loop add
Java, python, C,
whatsoever
Memory
hierarchy modelTiming model
Functional model
Step1
Step2
Step3
Step4
Functional with
instruction counts